Publications Luc Claesen 何慎諾
  • Conference Papers
  • Journal Articles
  • Patents
  • Book Chapters
  • Books

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    Conference Papers
    Aydin Guzel, Dilara Hisar, Luc Claesen, Fatih H. Ugurdag, “Fast Incremental Least Square Pose Estimation for Hardware Implementation with Rolling Shutter Camera “, 2020 28th Signal Processing and Communications Applications Conference (SIU), IEEE, p. 1 -4, DIO: https://doi.org/10.1109%2FSIU49456.2020.9302192

    Siang Chen, Kai Huang, Bowen Li, Dongliang Xiong, Haitian Jiang, Luc Claesen, "Adaptive Hybrid Composition Based Super-Resolution Network via Fine-Grained Channel Pruning", In: Bartoli A., Fusiello A. (eds) Computer Vision – ECCV 2020 Workshops. ECCV 2020. Lecture Notes in Computer Science, vol 12537. Springer, Cham. https://doi.org/10.1007/978-3-030-67070-2_7, pp. 119-135.

    Chen S., Huang K., Xiong D., Li B., Claesen L. (2020) "Fine-Grained Channel Pruning for Deep Residual Neural Networks", In: Farkaš I., Masulli P., Wermter S. (eds) Artificial Neural Networks and Machine Learning – ICANN 2020. ICANN 2020. Lecture Notes in Computer Science, vol 12397. Springer, Cham. https://doi.org/10.1007/978-3-030-61616-8_1, pp. 3-14

    Wout Swinkels, Luc Claesen, "Novel 3-DOF Simulated Annealing-Based Haptic Rendering Algorithm", Eurohaptics 2020, Leiden, 6/09/2020 - 9/09/2020.

    Michiel Darcis, Wout Swinkels, Aydin Emre Guzel, Luc Claesen, “PoseLab: A Levenberg-Marquardt Based Prototyping Environment for Camera Pose Estimation”, Proc. IEEE 11th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics (CISP-BMEI), Beijing, Oct 13-15, 2018, DOI: 10.1109/CISP-BMEI.2018.8633112

    Laurens Le Jeune, Wout Swinkels, Sun Yi, Constantinus Politis, Luc Claesen, “Analysis of collision detection using Implicit Sphere Tree in haptic interaction environments for maxillofacial surgery applications”, In: Li, Wei; Li, Qingli; Wang, Lipo (Ed.). Proceedings 2018 11th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics, IEEE Institute of Electrical and Electronics Engineers, Oct 13-15, 2018, DOI: 10.1109/CISP-BMEI.2018.8633199

    Wout Swinkels, Luc Claesen, Feng Xiao, Haibin Shen, "Real-time SVM-based Emotion Recognition Algorithm", Proceedings 2017 10th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics CISP-BMEI 2017, IEEE, Shanghai, ISBN 978-1-5386-1936-0, 14-16 October 2017, pp. 2A-13 - 2A-18

    Niels Pirotte, Casper Vranken, Wout Swinkels, Luc Claesen, Yi Sun, Constantinus Politis, "Haptic Collision Detection on Highly complex Medical Data Structures", Proceedings 2017 10th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics CISP-BMEI 2017, IEEE, Shanghai, ISBN 978-1-5386-1936-0, 14-16 October 2017, pp. 3B-7 - 3B-12.

    Michiel Darcis, Gert Leurs, Kenny Geens, Alexandra Jankelevitch, Wout Swinkels, Luc Claesen, "Automated Winston-Lutz Test for Efficient Quality Control in Stereotactic Radiosurgery", Proceedings 2017 10th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics CISP-BMEI 2017, IEEE, Shanghai, ISBN 978-1-5386-1936-0,  14-16 October 2017, pp. 3B-13 - 3B-18.

    Kobe Bamps, Céline Cuypers, Luc Claesen, Pieter Koopman, "CT-based Automatic Identification and Localization of the Right Phrenic Nerve", Proceedings 2017 10th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics CISP-BMEI 2017, IEEE, Shanghai, ISBN 978-1-5386-1936-0, 14-16 October 2017, pp. 4B-1 - 4B-6.

    Yanzhe Li, Kai Huang Kai, Luc Claesen, “High-Quality View Interpolation Based on Depth Maps and Its Hardware Implementation”, Proceedings of the 27th International Conference on Field-Programmable Logic and Applications, FPL-2017, IEEE Institute of Electrical and Electronics Engineers,p. 5B-1-5B-6. (International Conference on Field Programmable and Logic Applications).

    Wout Swinkels, Luc Claesen, Feng Xiao, Haibin Shen, "SVM Point-Based Real-time Emotion Detection.", Proceedings of the 2017 IEEE Conference on Dependable and Secure Computing, DSC-2017, Taipei - Taiwan, August 7-10, 2017, p. 86-92, DOI: 10.1109/DESEC.2017.8073838

    Kobe Bamps, Celine Cuypers, Pieter Polmans, Luc Claesen, Pieter Koopman, “Automatic Identification and Reconstruction of the Right Phrenic Nerve on Computed Tomography”, 10th Belgian Heart Rhythm Meeting, 5-7 October 2016, Brussels, Belgium (Poster).

    Wout Swinkels, Luc Claesen, Haibin Shen, “Camera-based Real-Time Emotion Classification Using Support-Vector Machines”, Proc. ICT.OPEN 2017,  Amersfoort, 21-22 March 2017.

    Yanzhe Li, Kai Huang, Luc Claesen, “SoC and FPGA Oriented High-quality Stereo Vision System”, Proceedings 26th International Conference on Field-Programmable Logic and Applications, SwissTech Convention Center Lausanne, Switzerland, 29 Aug - 2 Sept. 2016, Session S6a-2, pp. 1-4., DOI: 10.1109/FPL.2016.7577366

    Yanzhe Li, Kai Huang, Luc Claesen, “SoC Oriented Real-time High-quality Stereo VIsion System”, Proceedings IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, September 26-28, 2016, Tallinn, Estonia, Session 2b pp.1-6., DOI: 10.1109/VLSI-SoC.2016.7753558

    Bart Stukken, Yimu Wang, Yu Bao, Caikou Chen, Luc Claesen, “Comparison of Predictive-Corrective Video Coding Filters for Real-Time FPGA-based Lossless Compression in Multi-Camera Systems”, In: Lindh, Lennart; Mooney, Vincent J.; Roed, Ketil; Källberg, David; de Pablo, Santiago; Shalan, Mohamed; Ôberg, Johnny; Ellervee, Peeter (Ed.). 12th FPGAworld Conference: Academic Proceedings 2015, p. 33-39.

    Yufeng Lu, Luo Xiaohua, Yimu Wang, Luc Claesen, "Line Buffer Reduction for LUT-Based Real-time Image Inverse Warping", Proceedings 14th IEEE International New Circuits and Systems Conference NEWCAS-2016, Vancouver, pp. 1-4., DOI: 10.1109/NEWCAS.2016.7604780

    Po-Yen Chen, Chien Chen, Parthiban Selvaraj, Luc Claesen, “Poster: A Software-Defined Multi-Camera Network”, Proceedings of the 14th Annual International Conference on Mobile Systems, Applications, and Services Companion, Singapore, June 25-30, 2016, ACM MobiSys-2016, pp. 129-129, 10.1145/2938559.2938599

    Mi Zhang, Yimu Wang, Luc Claesen, Caikou Chen, "Structured Light Based Camera Calibration Methods for Computational Vision and Video", Proceedings ICT.OPEN 2016, Amersfoort, 22-23 March 2016.

    Wanqiu Zhang, Bart Stukken,Luc Claesen, Caikou Chen, "Low-Latency Lossless Video Compression Methods for Multi-camera Systems", Proceedings ICT.OPEN 2016, Amersfoort, 22-23 March 2016.

    Yimu Wang, Luc Claesen, "A Spatiotemporal Dithering Method to Extend Color Depth in Multi-Display System", Proc. 2nd International Conference on Systems and Informatics (ICSAI 2014), 15-17 November 2014, Shanghai, pp. 896-900. DOI: 10.1109/ICSAI.2014.7009412

    Wout Swinkels, Yi Sun, Bart Stukken, Constantinus Politis, Luc Claesen, "Cloud-based Collaboration Platform for Orthognathic Surgical Planning", Biomedica 2015 Genk, http://biomedicasummit.com/Biomedica2015/pdf/poster/M05.pdf, 2-3 June 2015

    Yu Bao, Bart Stukken, Jef Stals, Caikou Chen, Luc Claesen, “Quantitative Comparison of Lossless Video Compression for Multi-Camera Stereo and View Interpolation Applications.”, In: 13th IEEE International NEW Circuits and Systems Conference, Grenoble, France, 07-10 June 2015, DOI: 10.1109/NEWCAS.2015.7182116

    Wout Swinkels, Yi Sun, Bart Stukken, Constantinus Politis, Luc Claesen, "Cloud-based Orthognathic Surgical Planning Platform", Proceedings IEEE NEWCAS 2015 Conference, Grenoble, 7-10 June 2015, pp. 19B1-19B5, DIO: 10.1109/NEWCAS.2015.7182051

    Yu Bao, Jef Stals, Bart Stukken, Caikou Chen, Luc Claesen, "Hardware Efficient Quasi-Lossless Spatial Compression for Multi-Camera Computational Video Systems", Proceedings of the ICT.OPEN 2015 Conference, Amersfoort, The Netherlands, March 24-25, 2015. ISBN 978-90-73461-89-5

    Martijn Rymen, Chien-Hsin Chen, Chien Chen, Luc Claesen, “SDN Software Defined Network for High Bandwidth Multi-Camera Video Systems”, Proceedings of the ICT.OPEN 2015 Conference, Amersfoort, The Netherlands, March 24-25, 2015. ISBN 978-90-73461-89-5

    Zhengqiang Yu, Luc Claesen, Yun Pan, Andy Motten, Yimu Wang, Xiaolang Yan, “SoC Processor for Real-Time Object Labeling in Life Camera Streams with Low Line Level Latency”,  Proceedings IEEE International Symposium on Circuits and Systems, ISCAS-2014, Melbourne, Australia, 1-5 June 2014, pp. 345-348.  10.1109/ISCAS.2014.6865136

    Zhengqiang Yu, Luc Claesen, Yun Pan, Andy Motten, Yimu Wang, Xiaolang Yan, “SoC/FPGA Architecture for High-Speed Blob Detection”, ICT-Open 2013, Eindhoven, The Netherlands, 28-29 November 2013, paper presentation, ISBN 978-90-73461-84-0.

    Hu Jing-jin, Pan Yun, Yan Xiao-lang, Andy Motten, Luc Claesen, “Two-topology based high-level simulation platform for NoC performance evaluation”, 胡婧瑾 , 潘赟 , 严晓浪 , Andy Motten, Luc Claesen, “支持双拓扑结构的片上网络评估高层仿真平台”, 计算机应用研究, 2013, Vol.30 No. 9, Sept. 2013, pp. 2827-2830

    Yimu Wang, Alexander Peyls, Yun Pan, Luc Claesen, Xiaolang Yan, “Design of A Fast Self Organizing Map Accelerator”, Proceedings 7th FTRA International Conference on Multimedia and Ubiquitous Engineering (MUE 2013), Seoul, Korea, May 9-11, 2013.

    Fabrizio Farinelli, Andy Motten, Luc Claesen, “System-on-Chip Architecture for Real-Time License Plate Segmentation”, Proc. ICT.OPEN 2012 Conference, WTC Rotterdam, 22-23 October 2012.

    Andy Motten, Luc Claesen, “Trinocular Disparity Processor using a Hierarchical Classification Structure”, Proc. 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC), Oct. 7-10, 2012, Santa Cruz, USA, pp. 261-264.

    Andy Motten, Luc Claesen, Yun Pan, “Adaptive Memory Architecture for Real-Time Image Warping”, Proc. IEEE 30th International Conference on Computer Design (ICCD 2012), Sept. 30 - Oct. 3, 2012, Montreal Quebec, pp. 466-471.

    Luc Claesen, "System-on-Chip Design Challenges for Multi-Camera Computational Video", IEEE Fourth International Conference on Communications and Electronics ICCE-2012, Hue, Vietnam, August 1-3, 2012.  (Invited Presentation)

    Brecht Moris, Constantinus Politis, Yi Sun, Luc Claesen, "Automated tracking of the mandibular canal in CBCT images using matching and multiple hypotheses methods", Proc. IEEE Fourth International Conference on Communications and Electronics ICCE-2012, Hue, Vietnam, August 1-3, 2012, ISBN: 978-1-4673-2490-8, pp. 327-332.

    Luc Claesen, Andy Motten, Peter Vandoren, Tom Van Laerhoven, Frank Van Reeth, Yun Pan, Jingjin Hu, Ning Zheng, Xiaolang Yan, "Hardware/Software CoDesign of an Acceleration SoC for Interactive Digital Painting", Proc. IEEE Fourth International Conference on Communications and Electronics ICCE-2012, Hue, Vietnam, August 1-3, 2012, ISBN: 978-1-4673-2490-8, pp. 662-667.

    Andy Motten, Luc Claesen, Yun Pan, “Binary Confidence Evaluation for a Stereo Vision Based Depth Field Processor SoC”, Proc. first Asian Conference on Pattern Recognition IEEE, ACPR -2011,  Beijing, Nov. 28-30, 2011, pp. 456-460. 

    Andy Motten, Luc Claesen, “Real-Time Disparity Refinement Processor”, Proc. ICT.OPEN 2011, Veldhoven, 14 & 15 November 2011.

    Andy Motten, Luc Claesen, “Low-Cost Real-Time Stereo Vision Hardware With Binary Confidence Metric and Disparity Refinement“,  Proc. IEEE,  “The 2nd International Conference on Multimedia Technology”, Hangzhou, China, July 26-28, 2011, pp. 3559-3562.

    Andy Motten, Luc Claesen, "An On-Chip Parallel Memory Architecture for a Stereo-Vision System", Proc. 17th IEEE ICECS 2010, Athens, Dec. 12-15, 2010, IEEE Catalog Number: CFP10773-CDR, ISBN 978-1-4244-8156-9, pp. 500-503.

    Domien Nowicki, Luc Claesen, "SoC Architecture for Real-Time Interactive Painting based on Lattice-Boltzmann", Proc. 17th IEEE ICECS 2010, Athens, Dec. 12-15, 2010. IEEE Catalog Number: CFP10773-CDR, ISBN 978-1-4244-8156-9,  pp. 239-242.

    Andy Motten, Luc Claesen, "Real-Time Stereo Vision Hardware Architecture Suitable for Multiple Platforms", 3D Stereo Media Conference. The European 3D-Stereo Summit for Science, Technology, and Digital Art, Palais des Congrès Liège - Belgium, 8-10 December 2010, (4 pages)

    Domien Nowicki, Luc Claesen, "A Massively Parallel SoC Architecture for Real-Time Lattice-Boltzmann Fluid Dynamics Simulations", Proceedings of the STW.ict Conference - Workshop PROGRESS on Embedded Systems and Software, ISBN 978-90-73461-67-3, Veldhoven, November 18-19, 2010.

    Andy Motten, Luc Claesen, "An Efficient Parallel Memory Architecture for Window Based Video Processing", Proceedings of the STW.ict Conference - Workshop PROGRESS on Embedded Systems and Software, ISBN 978-90-73461-67-3, Veldhoven, November 18-19, 2010.

    Andy Motten, Luc Claesen, "A Binary Adaptable Window SoC Architecture for a StereoVision Based Depth Field Processor", Proc. IEEE VLSI-SOC 2010 Conference, Madrid, 27-29 Sept. 2010, pp. 25-30.

    Luc Claesen, Peter Vandoren, Tom Van Laerhoven, Andy Motten, Domien Nowicki, Tom De Weyer, Frank Van Reeth, Eddy Flerackers, "Smart Camera SoC System for Interactive Real-Time Real-Brush based Digital Painting Systems", Proc. IEEE VLSI-SOC 2010 Conference, Madrid, 27-29 Sept. 2010, pp. 247-252.

    Luc Claesen, Peter Vandoren, Tom Van Laerhoven, Andy Motten, Domien Nowicki, Frank Van Reeth, Eddy Flerackers, "Video Processing SoC for Low-Latency Real-Time Interactive Real-Brush Painting System", Proc. IEEE 18th VLSI-CAD 2010 Conference, Kaohsiung Taiwan, Aug. 3-6, 2010, pp. 367-370.

    Peter Vandoren, Luc Claesen, Tom Van Laerhoven, Johannes Taelman, Chris Raymaekers, Eddy Flerackers, Frank Van Reeth, "FluidPaint: an Interactive Digital Painting System using Real Wet Brushes"  Proc. of ITS2009, pp. 53 - 56, ACM, ISBN 978-1-60558-733-2, Nov. 2009.

    Peter Vandoren, Luc Claesen, Chris Raymaekers, Frank Van Reeth, "Reflections on enhancing interaction in surface computing using real-world objects"  Proc. of CHI'09 Workshop on Surface and Multitouch Computing, Apr. 2009.

    Peter Vandoren, Tom Van Laerhoven, Luc Claesen, Johannes Taelman, Chris Raymaekers, Frank Van Reeth, "IntuPaint: Bridging the Gap Between Physical and Digital Painting"  Proc. of TABLETOP 2008, pp. 71 - 78, IEEE, ISBN 978-1-4244-2897-7, Oct. 2008.  (Best Paper Award)

    Peter Vandoren, Tom Van Laerhoven, Luc Claesen, Johannes Taelman, Fabian Di Fiore, Frank Van Reeth, Eddy Flerackers, "DIP-IT: Digital Infrared Painting on an Interactive Table"  CHI '08 extended abstracts on Human factors in computing systems, pp. 2901 - 2906, ACM, ISBN 978-1-60558-012-X, Apr. 2008.

    Stefan Hendricx, L. Claesen, “Formally verified redundancy removal”, Proceedings, IEEE Design, Automation and Test in Europe Conference and Exhibition, 1999, pp. 150-155.

    Stefan Hendricx, L. Claesen, “Symbolic Multi-Level Verification and Refinement”, In Proceedings Ninth Great Lakes Symposium on VLSI 1999, GLSV’99, Ypsilanti MI, March 4-6, 1999, pp. 288-291.

    R. Martens, L. Claesen, “Utilizing Baum-Welch for on-line signature verification”, In Proceedings of the 6th Int. Workshop on Frontiers in Handwriting Recognition, pp. 389-397, 1998.

    Ekaterini Gikas, Stefan Hendricx, Luc Claesen, “Modeling Layout Extracted MOS Transistor Circuits in VHDL”, In IFIP Proceedings Forum on Design Languages FDL’98, Laussane September 6-11, 1998.

    Stefan Hendricx, Luc Claesen, "A Symbolic Core Approach to the Formal Verification of Integrated Mixed-Mode Applications", proceedings Electronic Design and Test Conference, IEEE Press, ED&TC'97, Paris, 17-20 March 1997,  pp. 432-436.

    Ronny Martens, Luc Claesen, "An evaluation of Different Handwriting Observation Techniques from a Signature Verification Point of View", In Proc. Of the 1st Brazilian Symposium on Document Image Analysis (ed. Nabeel A. Murshed and Flavio Bortolozzi), Springer-Verlag, pages 273-282. 1997

    R. Martens, L. Claesen, “On-line signature verification: Discrimination emphasized.” In Proc. Of the 4th Int. Conf. On Document Analysis and Recognition, Vol. 2, pp. 657-660, 18-20 Aug. 1997.

    R. Martens, L. Claesen, “Dynamic programming optimization for on-line signature verification.”, In Proceedings of the 4th IEEE Int. Conf. On Document Analysis and Recognition, Vol. 1, pages 653-656, 18-20 Aug.1997.

    L. Claesen, “Codesign”, Proc. IEEE DAK Forum 1996 and tutorials, 21-23 oktober 1996, Trondheim.

    O. Thiry, L. Claesen, "A Formal Verification Technique for Embedded Software", Proceedings IEEE International Conference on Computers and Design, ICCD'96, Austin Texas, 7-9 October 1996, pp. 352-357.

    R. Martens, L. Claesen, "On-line signature verification by dynamic time-warping", Proceedings 13th International Conference on Pattern Recognition, August 25-29, 1996, Vienna, Austria, pp. 38-42 (Vol. 1).

    F. Van Steenkiste, H. Grunkorn, L. Claesen, K. Baert, D. De Bruyker, V. Spiering, B. van der Schroot, P. Arquint and R. Born, "A micro sensor array for biochemical sensing", Proc. Eurosensors X Leuven, pp. 1337-1340, September 1996

    Stefan Hendricx, Luc Claesen, "A Symbolic Modeling Approach for the Formal Verification of Integrated Mixed Mode Systems", Proceedings 3rd Workshop on Designing Correct Circuits (DCC'96), September 2-4, 1996, Bstad, Sweden, pp. 1-12.

    L. Claesen, "Integrated Micro-system Design" - tutorial, SB-Micro conference, Aguas di Lindoya, Brazil, 29 July - 2 August 1996.

    L. Claesen, "Applied Formal Verification Methods" - tutorial, SB-Micro conference, Aguas di Lindoya, Brazil, 29 July - 2 August 1996.

    Ronny Martens, Luc Claesen, "Optimized Feature Extraction for On-line Signature Verification", In proceedings of the 9th Aachener Kolloquium “Signaltheorie and recognition” pages 305-308, 1997.

    L. Claesen, D. Beullens, R. Martens, R. Mertens, S. De Schrijver, W. De Jong, “SmartPen: An Application of Integrated Microsystem and Embedded Hardware/Software CoDesign”, proceedings U. F. Electronic Design and Test Conference, IEEE Press, ED&TC'96, Paris, 11-14 March 1996, pp. 201-205.

    L. Claesen, "SFG-Tracing: A practical formal verification method and its application to behavioral synthesis verification, Proceedings IFIP state-of-the-art Seminar on "Hardware Specification, Verification and Synthesis", January 10-11, 1996, Bangalore, India, pp. 205-287.

    L. Claesen, "Low Power Application to Integrated Micro-System Design", NATO Advanced Study Institute, August 20-30, 1996, Il Ciocco - Lucca, Italy.

    L. Claesen, "Advanced issues in high-quality low-power systems", NATO Advanced Study Institute; August 20-30, 1996, Il Ciocco - Lucca, Italy.

    L. Claesen, M. Genoe, “Multi-Level Formal Verification of High Level Synthesis: a Reality!”, Proceedings SASIMI-95, Synthesis and System Integration of MIxed Technologies, Nara Prefectural New Public Hall, Nara, Japan, 25-26 August 1995, pp. 106-113.

    M. Genoe, L. Claesen, H. De Man, “A Parallel Method for Functional Verification of Medium and High Throughput Digital Signal Processing Synthesis”, proceedings IEEE International Conference on Computer Design, VLSI in Computers & Processors, ICCD'94, Cambridge Massachusetts, October 10-12, 1994, pp. 460-463.

    C. Angelo, L. Claesen, “Reasoning about Linear Systems of Equations in HOL”, Proceedings International Conference on Higher Order Logic Theorem Proving and its Applications 1994, Malta, 19-22 September 1994.

    J. G. Samsom, L. J. M. Claesen, H. J. de Man, “SynGuide: An environment for interactive Correctness Preserving Transformations”, Proceedings 1993 IEEE Workshop on VLSI Signal Processing, Veldhoven, The Netherlands, October 20-22, 1993, pp. 269-277.

    J. Daemen, L. Claesen, M. Genoe, G. Peeters, R. Govaerts, J. Vandewalle, “A Cryptographic Chip for ISDN And High Speed Multi-Media Applications”, Proceedings 1993 IEEE Workshop on VLSI Signal Processing, Veldhoven, The Netherlands, October 20-22, 1993, pp. 12-20.

    L. Claesen, J. Daemen, M. Genoe, G. Peeters, “Subterranean: A 600 Mbit/sec Cryptographic VLSI Chip”, Proceedings ICCD'93, International Conference on Computer Design, VLSI in Computers & Processors, Cambridge Massachusetts, October 3-6, 1993. pp. 610-613.

    P. Johannes, L. Claesen, H. De Man, “Achieving accuracy and high performance in static sensitizable path analysis”, Proceedings ESSCIRC'93, Nineteenth European Solid-State Circuits Conference, Sevilla, Spain, 22-24 September 1993.

    P. Johannes, L. Claesen, “On the use of reconvergence analysis for efficient hierarchical static sensitizable path analysis”, Proceedings for TAU'93, 1993 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Malente FRG, September 14-16, 1993.

    J. Vandenbergh, L. Claesen, “Verification of Retiming Transformations”, Proceedings TAU'93, 1993 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Malente FRG, September 14-16, 1993.

    C. M. Angelo, L. Claesen, “Degrees of Formality in Shallow Embedding Hardware Descriptions in HOL”, Proceedings of the 1993 International Workshop on Higher Order Logic Theorem Proving and its Applications, Vancouver, Canada, August 11-13, 1993, pp. 89-100.

    L. Claesen, M. Genoe, E. Verlind, “Implementation/Specification Verification by means of SFG-Tracing”, CHARME-93, IFIP WG 10. 2 Advanced Research Working Conference on Correct Hardware Design Methodologies, 24-26 May, 1993, Arles (F).

    M. Genoe, L. Claesen, E. Verlind, H. De Man, “Formal Verification of High Level Synthesis by means of SFG-Tracing”, Proc. Sixth ACM/SIGDA & IEEE Workshop on High Level Synthesis, (editor: D. Gajski), Dana Point Resort, California, USA, November 4-6, 1992, pp. 336-343.

    C. Angelo, L. Claesen, H. De Man, “The formal semantics definition of a Multi-rate DSP Specification Language in HOL”, in Proceedings HOL'92 International workshop, IMEC Leuven Belgium, 21-24 September 1992, pp. 229-247.

    P. De Vijt, L. Claesen, H. De Man, “ASICs for a High Performance Multi Processor System for Photo-realistic Image Synthesis”, Proc. Seventh Workshop on Graphics Hardware, Eurographics 92, 7 Sept. 92, pp. 44 - 52.

    J. Vandenbergh, D. Verkest, L. Claesen, H. De Man, “Correct Library Development for High Level Application Oriented Synthesis in the CATHEDRAL environment”, Proc. IFIP workshop on Application Oriented Synthesis, Dresden, March 23-25, 1992.

    L. Claesen, “Formal Hardware Verification”, Tutorial at Workshop on Design Verification & Test, Roros Norway, March 11-13, 1992.

    H. Samsom, L. Claesen, H. De Man, “Correctness Preserving Transformations on the Hough Transform.” Proc. IEEE CompEuro-92 conference, The Hague, The Netherlands, 4-8 May, 1992, pp. 11-16.

    F. Proesmans, L. Claesen, E. Verlind, M. Genoe, H. De Man, “Verification Strategy of the CATHEDRAL-1 silicon compiler based on the SFG-Tracing methodology”, Proc. IEEE CompEuro-92 conference, The Hague, The Netherlands, 4-8 May, 1992, pp. 17-22.

    P. Johannes, L. Claesen, H. De Man, “SLOCOP: a tool for hierarchical timing verification and efficient delay characterization of synchronous circuits”, Proc. European Conference on Design Automation EDAC-92, Brussels, 16-19 March 1992, pp. 560.

    E. Verlind, L. Claesen, M. Genoe, F. Proesmans, “Partial Strength Ordering applied to Symbolic Switch-Level Analysis”, Proc. European Conference on Design Automation EDAC-92, Brussels, 16-19 March 1992, pp. 388-392.

    M. Genoe, L. Claesen, E. Verlind, F. Proesmans, H. De Man, “Automatic Formal Verification of Cathedral-II Circuits from Transistor Switch Level Implementations up to High Level Behavioral Specifications by the SFG-Tracing Methodology” Proc. European Conference on Design Automation EDAC-92, Brussels, 16-19 March 1992, pp. 54-58.

    D. Verkest, L. Claesen, H. De Man, “A proof of the Non Restoring Division algorithm and its implementation on the CATHEDRAL-II ALU”, Proc. 2nd IFIP Workshop on Designing Correct Circuits, ed. J. Staunstrup, R. Sharp, Lyngby, pp. 173-192.

    P. Johannes, L. Claesen, H. De Man, “On the use of hierarchy in timing verification with staticaly sensitizable paths”, VLSI, 1998, Proceedings of the Second Great Lakes Symposium, 28-29 Feb. 1992, pp. 4-8.

    M. Genoe, L. Claesen, F. Proesmans, E. Verlind, H. De Man, “Symbolic Analysis and Formal Verification of Digital Systems”, International Workshop on Symbolic Methods and Applications to Circuit Design., CNET, Bagneux, October 17-18, 1991.

    L. Claesen, M. Genoe, F. Proesmans, E. Verlind, H. De Man, “SFG-Tracing: a Multi-Level Formal Verification Methodology”, Workshop on Formal Verification for Hardware and Software, Organized by IMAG, Grenoble, October 7-8, 1991.

    L. Claesen, M. Genoe, E. Verlind, F. Proesmans, H. De Man, “Synthesis Verification by the SFG-Tracing Methodology”, IFIP International Workshop on Application of Synthesis and Simulation, Lenggries, Germany, August 25-28, 1991.

    L. Claesen, “Survey of Hardware Verification in HOL”, (tutorial summary), Proc. 1991 International Workshop on the HOL Theorem Proving System and Its Applications., IEEE Press, Davis CA, USA, August 1991.

    C. M. Angelo, D. Verkest, L. Claesen, H. De Man, “Formal Hardware Verification in HOL and in Boyer-Moore: A Comparative Analysis”, Proc. 1991 International Workshop on the HOL Theorem Proving System and Its Applications., IEEE Press, Davis CA, USA, August 1991, pp. 340-347.

    W. Ploegaerts, L. Claesen, H. De Man, “Defining Recursive Functions in HOL”, Proc. 1991 International Workshop on the HOL Theorem Proving System and Its Applications., IEEE Press, Davis CA, USA, August 1991, pp 358-366.

    L. Claesen, D. Borrione, H. Eveking, G. Milne, J. L. Paillet, P. Prinetto, “CHARME: Towards Formal Design and Verification for Provably Correct VLSI Hardware”, Proc. Advanced Research Workshop on Correct Hardware Design Methodologies, June 12-14, 1991, Turin, Italy, pp. 1-22.

    L. Claesen, M. Genoe, E. Verlind, F. Proesmans, H. De Man, “SFG-Tracing: a methodology of "Design for Verifiability"“, Proc. Advanced Research Workshop on Correct Hardware Design Methodologies, June 12-14, 1991, Turin, Italy, pp. 195-208.

    C. M. Angelo, D. Verkest, L. Claesen, H. De Man, “On the comparison of HOL and Boyer-Moore for formal hardware verification”, Proc. Advanced Research Workshop on Correct Hardware Design Methodologies, June 12-14, 1991, Turin, Italy, pp. 419-440.

    L. Claesen, E. Verlind, M. Genoe, F. Proesmans, H. De Man, “Multi-Level Digital Design Verification by SFG-Tracing”, Proc. 1991 European Conference on Circuit Theory and Design, ECCTD-91, Lyngby, Sept. 3-6, 1991, pp. 412-421.

    M. Genoe, L. Claesen, E. Verlind, F. Proesmans, H. De Man, “Illustration of the SFG-Tracing multi-level behavioral verification methodology, by the correctness proof of a high to low level synthesis application in CATHEDRAL-II”, Proceedings IEEE International Conference on Computers and Design 1991, ICCD-91, Cambridge Mass., October 14-16, 1991, pp. 338-341.

    L. Claesen, M. Genoe, E. Verlind, F. Proesmans, H. De Man, “Application Example of multi-level digital design verification by the SFG-Tracing Methodology”, Proceedings IEEE EUROASIC-91 conference, Paris, 27-31 May 1991, pp. 379-384.

    C. Angelo, L. Claesen, H. De Man, “A Methodology for Proving Correctness of Parameterized Hardware Modules in HOL”, Proc. Tenth International Symposium on Computer Hardware Description Languages and their Applications, CHDL-91, Marseille, April 22-24, pp. 63-82.

    L. Claesen, F. Proesmans, E. Verlind, H. De Man, “SFG-Tracing: a Methodology for the Automatic Verification of MOS Transistor Level Implementations from High Level Behavioral Specifications”, Proceedings ACM-SIGDA International Workshop on Formal Methods in VLSI Design, ed. P. A. Subrahmanyam, January 9-11, 1991.

    W. De Rammelaere, I. Bolsens, L. Claesen, H. De Man, “Derivation of Signal Flow Direction in MOS VLSI”, Proceedings IEEE, International Conference on Computers and Design, ICCD-90, September 1990, pp. 206-209.

    P. Lammens, L. Claesen, H. De Man, “Tautology Checking Benchmarks, Results with TC”, Formal VLSI Correctness Verification, ed. L. Claesen, ISBN 0 444 88688 5, North-Holland Elsevier Science Publishers, 1990, p. 95-100.

    D. Verkest, L. Claesen, H. De Man, “On the use of the Boyer-Moore theorem prover for correctness proofs of parameterized hardware modules”, Formal VLSI Specification and Synthesis, ed. L. Claesen, ISBN 0 444 88372 X, North-Holland Elsevier Science Publishers, 1990, p. 99-116.

    M. Genoe, W. Ploegaerts, L. Claesen, H. De Man, C. Tricarico, R. Delpretti, D. Dauw, “An ASIC for Die-Sinking Spark Erosion Simulations”, Proceedings EUROASIC-90, Paris, 29-31 May 1990.  pp. 236-239.

    P. Odent, L. Claesen, H. De Man, “A Combined Waveform relaxation - Waveform Relaxation Newton Algorithm for Efficient Parallel Circuit Simulation.“, Proc. European Design Automation Conference EDAC-90, Glasgow 12-15 March 1990, pp. 244-248.

    D. Verkest, L. Claesen, H. De Man, “Correctness proofs of parameterized hardware modules in the Cathedral-II synthesis environment”, Proc. European Design Automation Conference EDAC-90, Glasgow 12-15 March 1990, pp.  62-66.

    J. P. Schupp, J. Cockx, L. Claesen, H. De Man, “SPI: An Open Interface Integrating Highly Interactive CAD Tools”, Proc. European Design Automation Conference EDAC-90, Glasgow 12-15 March 1990, pp. 492-495.

    P. Johannes, P. Das, L. Claesen, H. De Man, “SLOCOP-II: A versatile timing system for MOSVLSI”, Proc. European Design Automation Conference EDAC-90, Glasgow 12-15 March 1990, pp. 528-523.

    J. P. Schupp, J. Cockx, L. Claesen, H. De Man, “SPI: A Practical and Open Interface for Electronic CAD Tool Integration”, Proceedings ESPRIT Conference 1989 Brussels, North-Holland Publ., 27-30 November 1989.

    P. Lammens, L. Claesen, H. De Man, “Tautology Checking Benchmarks, Results with TC”, Proc. IMEC-IFIP International Workshop on: Applied Formal Methods For Correct VLSI Design, Houthalen, 13-16 November 1989, pp. 600-604.

    D. Verkest, L. Claesen, H. De Man, “On the use of the Boyer-Moore theorem prover for correctness proofs of parameterized hardware modules”, Proc. IMEC-IFIP International Workshop on: Applied Formal Methods For Correct VLSI Design, 13-16 November 1989, Houthalen, pp. 405-422.

    P. Johannes, P. Das, L. Claesen, H. De Man: “SLOCOP-II: Improved accuracy and efficiency in timing verification, based on logic functionality and MOS circuit hierarchy”, Proceedings ESSCIRC-89, Vienna Austria, September 20-22, 1989.

    W. Ploegaerts, D. Verkest, L. Claesen, H. De Man, “Description and Verification of Regular Structures using a Functional Hardware Description Language”, EUROMICRO-89, Cologne, Sept. 4-8, 1989, pp. 279-286.

    L. Claesen, R. T. Boute, J. De Man, W. Ploegaerts, M. Seutter, J. Vanslembroek, D. Verkest, “Application of System Semantics to VLSI for the Transformational Design of a Parameterized Booth Multiplier Module -a case study-”, Proc. EUROMICRO-89, Cologne, Sept. 4-8, 1989, pp. 261-266.

    P. Lammens, L. Claesen, H. De Man, “Correctness Verification of VLSI Modules Supported by a Very Efficient Boolean Prover”, Proc. IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD-89, Cambridge Massachusetts, Oct. 2-4, 1989, pp. 266-269.

    P. Odent, L. Claesen, H. De Man, “Feedback loops and large subcircuits in the multiprocessor implementation of a relaxation based circuit simulator”, Proc. 26th Design Automation Conference, DAC-89, Las Vegas, 25-29 June 1989, pp. 25-30.

    S. Perremans, L. Claesen, H. De Man, “Static Timing Analysis of Dynamically Sensitizable Paths”, Proc. 26th Design Automation Conference, DAC-89, Las Vegas, 25-29 June 1989, pp. 568-573.

    I. Bolsens, W. De Rammelaere, L. Claesen, H. De Man, “Electrical debugging of synchronous MOS VLSI circuits exploiting analysis of the intended logic behavior”, Proc. 26th Design Automation Conference, DAC-89, Las Vegas, 25-29 June 1989, pp. 513-518.

    P. Das, P. Johannes, L. Claesen, H. De Man, “Hierarchical timing view generation including accurate modeling for false paths.” Proceedings IEEE Custom Integrated Circuits Conference, CICC-89, San Diego, 15-18 May, 1989, pp. 13. 3. 1-13. 3. 4.

    P. Odent, L. Claesen, H. De Man, “New parallel techniques for simulating MOS circuits with waveform relaxation algorithms in CSWAN”, Proceedings IEEE 1989 International Symposium on Circuits and Systems, ISCAS-89 Portland, Oregon, 9-11 May 1989, pp. 1166-1169.

    D. Verkest, P. Johannes, L. Claesen, H. De Man, “Program Transformations of Hardware Descriptions by means of ILP”, Proceedings IEEE 1989 International Symposium on Circuits and Systems, ISCAS-89 Portland, Oregon, 9-11 May, 1989, pp. 1174-1177.

    L. Claesen, J. P. Schupp, H. De Man, “Accelerated Sensitizable Path Algorithms for Timing Verification based on Code Generation”, Proceedings IEEE 1989 International Symposium on Circuits and Systems, ISCAS-89 Portland, Oregon, 9-11 May, 1989, pp. 885-888.

    I. Bolsens, W. De Rammelaere, L. Claesen, H. De Man, “Expert Analysis of Synchronous Digital MOS Circuits Using Rule Based Programming And Symbolic Analysis”, Proceedings ESPRIT conference, North-Holland Publ., Brussels, 14-18 Nov. 1988., pp. 269-282.

    E. Vanden Meersch, L. Claesen, H. De Man, “Accurate Timing Verification Algorithms for Synchronous MOS Circuits”, Proceedings ESPRIT conference, North-Holland Publ., Brussels, 14-18 Nov. 1988., pp. 283-302.

    I. Bolsens, W. De Rammelaere, L. Claesen, H. De Man, “Electrical verification using rule based programming and symbolic analysis”, proceedings IFIP workshop on Knowledge Based Systems for Test and Diagnosis, Institut National Polytechnique de Grenoble, France, September 27-29, 1988, pp. 186-205.

    D. Verkest, P. Johannes, L. Claesen, H. De Man, “Formal Techniques for Proving Correctness of Parameterized Hardware using Correctness Preserving Transformations”, Proceedings IFIP WG 10.2 International Working Conference on: “The Fusion of Hardware Design and Verification”, Glasgow, July 4-7, 1988, edited by G. Milne, North-Holland Publish, pp. 75-96.

    I. Bolsens, W. De Rammelaere, C. Van Overloop, L. Claesen, H. De Man, “A formal approach towards electrical verification of synchronous MOS circuits”, Proceedings 1988 IEEE International Symposium on Circuits and Systems, ISCAS-88, Espoo, Finland, June 7-9, 1988, pp. 2113-2116.

    E. Vanden Meersch, L. Claesen, H. De Man, “Automated Analysis of Timing Faults in Synchronous MOS Circuits”, Proceedings 1988 IEEE International Symposium on Circuits and Systems, ISCAS-88, Espoo, Finland, June 7-9, 1988, pp. 487-490.

    L. Claesen, F. Catthoor, D. Lanneer, G. Goossens, S. Note, J. Van Meerbergen, H. De Man, “Automatic Synthesis of Signal Processing Benchmark using the CATHEDRAL Silicon Compilers.”, Proceedings IEEE Custom Integrated Circuits Conference, CICC-88, Rochester, New York, May 16-19, 1988, pp. 14. 7. 1-14. 7. 4

    I. Bolsens, W. De Rammelaere, L. Claesen, H. De Man, “Expert Analysis of Synchronous Digital MOS Circuits Using Rule Based Programming And Symbolic Analysis”, presented at IEEE COMPEURO-88 Conference, Brussels, April 11-14, 1988.

    P. Lammens, L. Claesen, H. De Man, “TC: A LISP Tautology-Checker the kernel of a functional verification system for combinatorial logic”, presented at IEEE COMPEURO-88 Conference, Brussels, April 11-14, 1988.

    L. Claesen, P. Johannes, D. Verkest, H. De Man, “Guided Synthesis and Formal Verification Techniques for Parameterized Hardware Modules”, Proceedings IEEE COMPEURO-88 Conference, Brussels, April 11-14, 1988, pp. 90-99.

    L. Claesen, “Automatic Synthesis of Signal Processing Benchmark using Bit-Serial, Customized Processor and Bit-Sliced Architectures with the CATHEDRAL Silicon Compilers”, ACM-IEEE Workshop on High-Level Synthesis, Orcas Island, Eastsound, Washington, January 24-27, 1988.

    L. Claesen, Ph. Reynaert, G. Schrooten, J. Cockx, H. De Man, R. Severyns, P. Six: “Open Framework of Interactive and Communicating  CAD tools”, IFIP WG 10. 2 workshop on “Tool Integration and Design Environments, Paderborn FRG, November 26-27, 1987.

    J. Benkoski, E. Vanden Meersch, L. Claesen, H. De Man, “Efficient Algorithms for Solving the False Path Problem in Timing Verification”, Digest of Technical Papers: IEEE International Conference on Computer-Aided Design, ICCAD-87, Santa Clara, CA, Nov. 9-12, 1987, pp. 44-47.

    H. De Man, J. Rabaey, P. Six, L. Claesen, “Computer Aided Synthesis of Digital Signal Processing ASICs”, Journees d'Electronique 1987 (Application Specific Integrated Circuits (ASIC's)), pp. 121-137, Lausanne, Switzerland, October 6-8, 1987.

    L. Claesen, H. De Man, I. Bolsens, W. De Rammelaere, D. Dumlugol, P. Lammens, P. Odent, R. Severyns, E. Vanden Meersch, “Electrical, Timing and Behavioral Verification in the Meet-in-the-Middle MOSVLSI Design Environment of CATHEDRAL-II”, Proceedings IEEE International Conference on Computer Design: VLSI in Computers & Processors, ICCD-87, Rey Brook, New York, Oct. 5-8, 1987, pp. 142-145.

    L. Claesen, Ph. Reynaert, G. Schrooten, J. Cockx, I. Bolsens, H. De Man, R. Severyns, P. Six, E. Vanden Meersch, “Open System Architecture of an Interactive CAD Environment for Parameterized VLSI Modules”, Proceedings of the 4th Annual ESPRIT Conference, Brussels, Sept. 28-29, 1987, North-Holland, pp. 251-270.

    L. Claesen, F. Catthoor, H. De Man, J. Vandewalle, S. Note, K. Mertens, “A CAD environment for the thorough analysis, simulation and characterization of VLSI implementable DSP systems”, Proceedings IEEE International Conference on Computer Design: VLSI in Computers, ICCD-86, Port Chester, New York, October 6-9, 1986, pp. 72-75.  

    H. De Man, J. Rabaey, P. Six, L. Claesen, “ESPRIT 97: Towards a Silicon Compilation System for VLSI Digital Signal Processing”, ESPRIT Conference, Status Report of Ongoing Work, Brussels, Sept. 28-Oct. 10, 1986.

    E. Vanden Meersch, L. Claesen, H. De Man, “SLOCOP: A Timing Verification Tool for Synchronous CMOS Logic”, Proceedings of the ESSCIRC'86 Conference, Delft, The Netherlands, September 16-18, 1986, pp. 205-207.

    P. Six, L. Claesen, J. Rabaey, H. De Man, “An Intelligent Module Generator Environment”, Proceedings of the 23rd Design Automation Conference, Session 41. 3, pp. 730-735, Las Vegas, June 29-July 2, 1986.

    L. Claesen, S. Note, K. Mertens, H. De Man, “Flexible and efficient bit-parallel level simulation of hardware implementable digital signal processing systems”, Proceedings IEEE International Symposium on Circuits and Systems, ISCAS-86, San Jose CA, May 5-7, 1986, pp. 871-874.

    R. Jain, F. Catthoor, J. Vanhoof, B. Deloore, G. Goossens, N. Goncalves, L. Claesen, J. Van Ginderdeuren, J. Vandewalle, H. De Man, “Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using computer-aided design system”, ESPRIT technical week, Commission of the European Communities, Status Report of Ongoing Work 1985, North Holland Publishing Co., pp. 117-134, Sept. 23-25, 1985.

    R. Jain, G. Goossens, L. Claesen, J. Vandewalle, H. De Man, L. Gazsi, A. Fettweis, “CAD tools for the optimized design of VLSI wave digital filters”, Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP'85, Florida, March, 1985, pp. 1465-1468.

    H. De Man, J. Vandewalle, F. Catthoor, L. Claesen, B. De Loore, N. Goncalves, R. Jain, B. Schaballie, J. Van Ginderdeuren, “A unified box of CAD tools for the design of dedicated signal processing chips”, Proceedings of the IEEE International Conference on Computer Design: VLSI in computers, pp. 838-841, New York, October 8-11, 1984.

    H. De Man, J. Vandewalle, F. Catthoor, L. Claesen, B. De Loore, N. Goncalves, R. Jain, B. Schaballie, J. Van Ginderdeuren, “Advanced Algorithms, Architectures and Layout Techniques for Dedicated Digital Signal Processing Chips”, ESPRIT-84: Status Report of Ongoing Work, Brussels, Elsevier Science Publishers B. V. (North Holland), 1985, pp. 45-58.

    L. Claesen, J. Vandewalle, H. De Man, “General bounds on parasitic oscillations in arbitrary digital filters and their application in CAD”, Proceedings IEEE International Symposium on Circuits and Systems, ISCAS'84, Montreal, May 7-10, 1984, pp. 747-750.

    L. Claesen, H. De Man, J. Vandewalle, “DIGEST: A powerful design and evaluation CAD-tool for MOSVLSI implementation of digital filters”, Proceedings European Solid State Circuits Conference ESSCIRC'83, Lausanne, pp. 155-158, Sept. 1983.

    L. Claesen, H. De Man, J. Vandewalle, “Delay Management Algorithms for Digital Filter Implementations”, Proceedings European Conference on Circuit Theory and Design ECCTD'83, Stuttgart, Sept. 1983, pp. 479-482.

    J. Vandewalle, H. De Man, J. Rabaey, L. Claesen, “A pictorial derivation of the signal processing mechanism of multiphase switched capacitor networks”, Proc. IEEE Int. Symp. on Circuits and Systems, ISCAS-82, Rome, pp. 25-28, 1982.

    H. De Man, J. Rabaey, L. Claesen, J. Vandewalle, “DIANA-SC: A complete CAD system for switched capacitor filters”, Proc. European Solid State Circuits Conference ESSCIRC, Freiburg, 1981, pp. 130-133.

    L. Claesen, J. Rabaey, H. De Man, J. Vandewalle, “Examples of Analysis of SC-circuits with DIANA”, Proc. of the 1981 European Conf. on Circuit Theory and Design, The Hague, pp. 1073-1074, 1981.

    L. Claesen, H. De Man, J. Rabaey, J. Vandewalle, “An overview of CAD techniques for switched capacitor networks”, Proc. of the 1981 European Conf. on Circuit Theory and Design, The Hague, pp. 486-492, 1981.

    H. De Man, L. Claesen, J. Rabaey, J. Vandewalle, “Computer aided design of switched capacitor circuits using the DIANA program”, 37 pages, “Summer Course on Switched Capacitor Circuits S2C3”, Vol. I and II, edited by J. Vandewalle K.U. Leuven, Belgium, June 9-12, 1981.

    L. Claesen, J. Vandewalle, H. De Man, “Efficient computer analysis of switched capacitor circuits via the z-domain”, 39 pages, “Summer Course on Switched Capacitor Circuits S2C3”, Vol. I and II, edited by J. Vandewalle K.U. Leuven, Belgium, June 9-12, 1981.

    J. Vandewalle, L. Claesen, H. De Man, “A very efficient computer algorithms for direct frequency, aliasing and sensitivity analysis of switched capacitor  networks”, Proc. IEEE ISCAS Conference, Chicago, pp. 864-867, 1981.

    H. De Man, L. Claesen, J. Van Ginderdeuren, L. Darcis: ”A structured multiplier-free digital filter building block for LSI implementation”, Proceedings European Conference on Circuit Theory and Design, ECCTD'80, Warsaw, Sept. 1980, pp. 527-532.

    Journal Articles

    Kai Huang, Siang Chen, Bowen Li, Luc Claesen, Hao Yao, Junjian Chen, Xiaowen Jiang, Zhili Liu, Dongliang Xiong, “Structured precision skipping: Accelerating convolutional neural networks with budget-aware dynamic precision selection”, Journal of Systems Architecture, Vol. 124, March 2022, 102403, https://doi.org/10.1016/j.sysarc.2022.102403

    Siang Chen, Kai Huang, Bowen Li, Dongliang Xiong, Haitian Jiang, Luc Claesen, “Adaptive Hybrid Composition Based Super-Resolution Network via Fine-Grained Channel Pruning”, Lecture notes in computer science, 12537, p. 119 -135, DIO: https://doi.org/10.1007%2F978-3-030-67070-2_7

    Kai Huang, Siang Chen, Bowen Li, Luc Claesen, Hao Yao, Junjian Chen, Xiaowen Jiang, Zhili Liu, Dongliang Xiong, “Acceleration-aware Fine-grained Channel Pruning for Deep Neural Networks via Residual Gating”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30 June 2021, DIO: 10.1109/TCAD.2021.3093835

    Qi Wang, Jinxiang Lai, Luc Claesen, Zhengguo Yang, Liang lei, Wenyin Liu. "A Novel Feature Representation: Aggregating Convolution Kernels for Image Retrieval". Neural Networks Vol. 130, October 2020, Elsevier, pp 1-10. Doi: 10.1016/j.neunet.2020.06.010.

    A.J. Lungu, W. Swinkels, L. Claesen, P. Tu, J. Egger, X.J. Chen, "A review on the applications of virtual reality, augmented reality and mixed reality in surgical simulation: an extension to different kinds of surgery", Expert Review of Medical Devices, Volume 18, 2021, Issue 1, pp. 47-62, 16 Dec. 2020. https://doi.org/10.1080/17434440.2021.1860750

    Yanzhe Li, Luc Claesen, Kai Huang, Menglian Zhao, “A Real-Time High-Quality Complete System for Depth Image-Based Rendering on FPGA”, IEEE Transactions on Circuits and Systems for Video Technology, Print ISSN: 1051-8215, Online ISSN: 1558-2205, dio: 10.1109/TCSVT.2018.2825022, 2018, April 2019, Volume 29, Issue 4, pp. 1179-1193.

    Pieter Koopman, Kobe Bamps, Celine Cuypers, Luc Claesen, “Automatic identification and reconstruction of the right phrenic nerve on computed tomography”, In: ACTA CARDIOLOGICA, 72(5), 2017, p. 580.

    A. Motten, L. Claesen, “Low-Cost Real-Time Stereo Vision Hardware with Binary Confidence Metric and Disparity Refinement”, International Journal of Multimedia Technology, World Academic Publishing, Vol. 1 No. 2, 2011, p. 70-77, ISSN: 2225-1456

    R. Martens, L. Claesen, “Incorporating local consistency into the online signature verification process”, International Journal on Document Analysis and Recognition, pp. 110-115, 1998.

    G. Beenker, L. Claesen, H. Eveking et al. “The Practical Application of Formal Verification”, IEEE Design & Test of Computers, Vol 12, Issue 3, 1995, pages: 96-102. 

    C. M. Angelo, L. Claesen, H. De Man, “Modeling Multi-rate DSP Specification Semantics for Formal Transformational Design in HOL”, Formal Methods in System Design - An International Journal, Kluwer Academic Publishers, Volume 5, Number 2, July 1994, pp. 61-94.

    C. M. Angelo, D. Verkest, L. Claesen, H. De Man, “On the Comparison of HOL and Boyer-Moore for Formal Hardware Verification”, Formal Methods in System Design - An International Journal, Kluwer Academic Publishers, Volume 2, Number 1, February 1993, pp. 45-72.

    D. Verkest, L. Claesen, H. De Man, “A Proof of the Non Restoring Division algorithm and its implementation on an ALU”, in Formal Methods in System Design, Kluwer Academic Publishers, Volume 4, Number 1, January 1994, pp. 5-32.

    D. Verkest, L. Claesen, H. De Man, “Transformational Design Methodology for Parameterized VLSI Modules”, International Journal of Computer Aided VLSI Design, special issue on VLSI Design Methodologies for Signal Processing Architectures, Vol. 3, No. 1, 1991, pp. 9-41.

    P. Odent, L. Claesen, H. De Man, “Acceleration of Relaxation Based Circuit Simulation using a Multi-Processor System”, IEEE Transactions on Computer Aided Design of Circuits and Systems, Vol. 9. No. 10, October 1990, pp. 1063-1072.

    J. Benkoski, E. Vanden Meersch, L. Claesen, H. De Man, "Timing Verification using Statically Sensitizable Paths", IEEE Transactions on Computer Aided Design of Circuits and Systems., Vol. 9, No. 10, October 1990, pp. 1073-1084.

    L. Claesen, J. -P. Schupp, P. Das, P. Johannes, S. Perremans, H. De Man, “Efficient False Path Elimination Algorithms for Timing Verification by Event Graph Preprocessing”, Integration, the VLSI Journal, North Holland, Volume 8, Number 2, November 1989, pp. 173-187.

    H. De Man, J. Rabaey, J. Vanhoof, G. Goossens, P. Six, L. Claesen, “CATHEDRAL II: A  Computer Aided Synthesis System for Digital Signal Processing VLSI Systems”, IEE Computer-Aided Engineering Journal, Volume 5 Issue 2, April 1988, pp. 55-66.

    H. De Man, J. Rabaey, P. Six, L. Claesen, “CATHEDRAL-II: A Silicon Compiler for Digital Signal Processing Multiprocessor VLSI Systems”, IEEE Design & Test of Computers, Vol. 3, Nr. 6, December 1986, pp. 13-26.

    R. Jain, F. Catthoor, J. Vanhoof, B. Deloore, G. Goossens, N. Goncalves, L. Claesen, H. Van Ginderdeuren, J. Vandewalle, H. De Man, “Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer aided design system”, Joint special issue of the IEEE transactions on Circuits and Systems Vol. CAS-33, No. 2, pp. 183-195, February 1986, and the IEEE Journal of Solid-State Circuits Volume SC-21, No. 1, pp. 73-85, February 1986, on VLSI analog and digital signal processing.

    L. Claesen, H. De Man, J. Vandewalle, “DIGEST: a digital filter evaluation and simulation tool for MOSVLSI implementations”, IEEE Journal of Solid State Circuits, Vol. SC-19, No. 3, June 1984, pp. 414-424.

    L. Claesen, H. De Man, J. Vandewalle, J. Rabaey, “DIANA. SC a versatile top-down analysis tool for switched capacitor circuits”, Microelectronics Journal, Vol. 14, No. 2, March/April 1983, pp. 37-53.

    L. Claesen, J. Vandewalle, H. De Man, “Efficient computer analysis of switched-capacitor circuits using matrix compaction techniques.”, The International Journal for Circuit Theory and Applications, Vol. 11., 1983, pp. 241-264.

    L. Claesen, “ED&TC 1995: Simulation versus formal verification”, IEEE Design & Test of Computers, Volume 12, Number 2, pp. 82, 1995.
     

    Books
    L. Claesen, R. Reis (Editors), "VLSI – Systems on Silicon", IFIP International Conference on Very Large Scale Integrated Systems, Chapman-Hall Science Publishers, 1997.

    "Computer Hardware Description Languages and their Applications", D. Agnew, L. Claesen, R. Camposano (Editors), Elsevier North-Holland, ISBN: 0 444 81641 0, 1993.

    "Higher Order Logic Theorem Proving and its Applications", L. Claesen, M. Gordon (Editors), Elsevier Science Publishers, North-Holland, ISBN 0 444 89880 8, 1993.

    D. Agnew, L. Claesen, R. Camposano (Editors), "Proceedings for CHDL'93", IFIP International Conference on Computer Hardware Description Languages and their Applications, published by OCRI Ottawa April 1993.

    L. Claesen, “Multi-Level Paradigms for Correct Design and Verification of Digital Systems”, Academia Analecta, Verhandelingen, Royal Academy of Belgium, 1992.

    L. Claesen, M. Gordon (Editors), "Proceedings for HOL'92", IMEC International Workshop, 21-24 September 1992, IMEC Leuven.

    L. Claesen (editor), "Formal VLSI Specification and Synthesis", Elsevier Science Publishers, North Holland, ISBN 0 444 88372 X, 1990.

    L. Claesen (editor), "Formal VLSI Correctness Verification", L. Claesen (editor), Elsevier Science Publishers, North Holland, ISBN 0 444 88688 5, 1990.

    L. Claesen, (editor), “Knowledge Based Design Assistant for Modular VLSI Design” Proceedings ESPRIT 1058 Workshop, IMEC, Kapeldreef, 75, B-3030 Leuven, Belgium. January 30-31, 1990.

    L. Claesen, (editor), “Applied Formal Methods For Correct VLSI Design”, Proceedings IMEC-IFIP International Workshop, 13-16 November 1989, 2 Volumes, IMEC Leuven Belgium.

     L. Claesen, (editor), “CAD for Digital Signal Processing”, Workshop Proceedings, 2 Volumes, IMEC, Kapeldreef, 75, B-3030 Leuven, Belgium. September 9-12, 1987.
     

    Patents
    “Apparatus and Method for Signal Classification and Signature Verification”, US Application No. 09/580,244, filed on May 26, 2000, (together with R. Martens).

      Thesis
    Luc, Claesen, "Computer Aided Design" of Integrated Systems of Digital and Analog Signal Processing", Ph.D. thesis KULeuven, March 1984.

    Book Chapters
    Yanzhe Li, Kai Huang, Luc Claesen, "A Novel Hardware-Oriented Stereo Matching Algorithm and Its Architecture Design in FPGA",  in "System-on-Chip in the Nanoscale Era - Design, Verification and Reliability" (editors:  Thomas Hollstein, Jaan Raik, Ian O’Connor, Anton Tšertov, Sergei Kostin, Elsevier Publishers, ISBN: 978-3-319-67103-1, 2017, pp. 213-232

    Yimu Wang, Alexander Peyls, Yun Pan, Luc Claesen, Xiaolang Yan, “Design of A Fast Self Organizing Map Accelerator for Handwritten Digit Recognition”, in “Multimedia and Ubiquitous Engineering” (editor: J.H. Park et al.), Lecture Notes in Electrical Engineering, 240, Springer Science + Business Media, DOI: 10.1007/978-94-007-6738-6_23, 2013, pp. 177-183.

    A. Motten, L. Claesen, Y. Pan, "Trinocular Stereo Vision using a Multi Level Hierarchical Classification Structure", chapter in "VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design”, editors: A. Coskun, A. Burg, R. Reis, M. Guthaus, Volume 418, 2013, Springer ISBN 978-3-642-45072-3, pp. 45-63.

    L. Claesen, P. Vandoren, T. Van Laerhoven, A. Motten, F. Di Fiore, F. Van Reeth, J. Liao, J. Yu, “Smart Camera System-on-Chip Architecture for Real-Time Brush Based Interactive Painting Systems”, Chapter in book “VLSI-SoC: Forward-Looking Trends in IC and System Design”, ed.  J.L. Alyala, D. Atienza, R. Reis, Springer Publishing, ISBN 978-3-642-28565-3, pp. 339-353. 2010

    S. Hendrickx, L. Claesen, “Verification of Finite-State-Machine Refinements Using a Symbolic Methodolgy”,  in “Correct Hardware Design and Verification Methods”, ed. L. Pierre, T. Kropf, Vol. 1703/1999, 1999.

    R. Martens, L. Claesen, “Utilizing Baum-Welch for On-line Signature Verification”, in “Advances in Handwriting Recognition” (ed. Seong-Whan Lee), World Scientific Publishing Co. Pte. Ltd. ISBN 981-02-3715-4. pp. 549-558, 1999.

    L. Claesen, H. De Kuyper, R. Tits, "Low Power Applications at System Level" in "Low Power Design in Deep Submicron Electronics", (ed. W. Nebel, J. Mermet), NATO-ASI Series E: Applied Sciences, Vol. 337, Kluwer Academic Publishers, ISBN 0-7923-4569-X, pp. 543-564.  1997.

    C. Angelo, L. Claesen, H. De Man, “The Formal Semantics Definition of a Multi-Rate DSP Specification Language in HOL”, in Higher Order Logic Theorem Proving and its Applications, A-20, Ed. L. Claesen, M. Gordon, Elsevier Science Publishers B. V. (North-Holland), ISBN: 0-444-89880-8, 1993, pp. 375-394.

    C. M. Angelo, D. Verkest, L. Claesen, H. De Man, “A Synopsis on the comparison of HOL and Boyer-Moore for Formal Hardware Verification”, in Correct Hardware Design Methodologies, (eds. P. Prinetto, P. Camurati), 1992 Elsevier Science Publishers B. V., ISBN: 0 444 893679, pp. 421-426.

    L. Claesen, M. Genoe, E. Verlind, F. Proesmans, H. De Man, “SFG-Tracing: a methodology of “Design for Verifiability”, in Correct Hardware Design Methodologies, (eds. P. Prinetto, P. Camurati), 1992 Elsevier Science Publishers B. V., ISBN: 0 444 893679, pp. 187-202.

    L. Claesen, D. Borrione, H. Eveking, G. Milne, J. L. Paillet, P. Prinetto, “CHARME: Towards Formal Design and Verification for Provably Correct VLSI Hardware”, in Correct Hardware Design Methodologies, (eds. P. Prinetto, P. Camurati), 1992 Elsevier Science Publishers B. V., ISBN: 0 444 893679, pp. 3-25.

    D. Verkest, L. Claesen, H. De Man, “An introduction to formal verification of parameterized VLSI hardware modules using the Boyer-Moore theorem prover”, chapter in book Formal Verification Techniques in VLSI Design ed. P. Camurati, P. Prinetto, Ablex Publishers, 1992.

    P. Johannes, L. Claesen, H. De Man, "Performance through hierarchy in static timing verification", in Algorithms, Software, Architecture, (ed. J. van Leeuwen), Elsevier Science Publishers B.V., 1992, pp. 703-709.

    D. Verkest, J. Vandenbergh, L. Claesen, H. De Man, “A Description Methodology for Parameterized Modules in the Boyer-Moore Logic”, in Theorem Provers in Circuit Design, (Ed. V. Stavridou, T. F. Melham, R. T. Boute), Elsevier North-Holland, ISBN: 0-444-89686-4, 1992, pp. 37-57.

    L. Claesen, M. Genoe, “SFG-Tracing: a Methodology for the Automatic Verification of MOS Transistor Level Implementations from High Level Behavioral Specifications”, Chapter in book edited by ed. P. A. Subrahmanyam, Lecture Notes in Computer Science, Springer-Verlag, 1995.

    L. Claesen, D. Borrione, H. Eveking, G. Milne, J. L. Paillet, P. Prinetto, “Turning the Formal Verification of VLSI Hardware into Reality”, Proceedings ESPRIT conference 1991, Brussels, North-Holland Publ, November 25-29 1991, pp. 857-873.

    P. De Worm, R. Severyns, L. Marent, A. Demar?e, J. Cockx, Ph. Reynaert, L. Claesen, H. De Man, P. Six, “SPI: A Procedural Interface for Electronic CAD Tool Integration”, in Electronic Design Automation Frameworks ed. R. Waxman, F. Rammig, North-Holland, Elsevier Science Publishers, 1991.

    L. Claesen, R. Severyns, P. Six, W. De Rammelaere, H. De Man, “Open Framework of Interactive and Communicating CAD tools.”, in “Tool integration and design environments” edited by F. J. Rammig, North-Holland Publ., Elsevier Science Publishers. B. V. (North-Holland), 1988, pp. 133-155.