Publication List

(A) Refereed Journal Papers

1.        1.   Tai-Cheng Lee, Yih-Lang Li, “Incremental Timing-Driven Placement with Approximated Sign-Off Wire Delay and Regression-based Cell Delay”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), VOL. 27, NO. 10, pp. 2434 – 2446, OCT 2019.

2.        Hsueh-Ling Yu, Yih-Lang Li, Tzu-Yi Liao, Tianchen Wang, Shu-Fei Tsai, and Yiyu Shi, “Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated Circuits”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume:26, Issue 5, pp. 912 – 923, May 2018.

3.        Hong-Yan Su, Chieh-Chu Chen, Yih-Lang-Li, An-Chun Tu, Chuh-Jen Wu and Chen-Ming Huang, “A Novel Fast Layout Encoding Method for Exact Multi-Layer Pattern Matching with Prüfer-Encoding”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume:34 , Issue: 1, pp. 95-108, 2015.

4.        Wen-Hao Liu and Yih-Lang Li, "Optimizing the Antenna Area and Separators in Layer Assignment of Multi-Layer Global Routing", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, Issue: 4, pp. 613 – 626, Apr 2014.

5.        Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, and Kai-Yuan Chao, “NCTU-GR 2.0: Multi-Threaded Collision-Aware Global Routing with Bounded-Length Maze Routing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 32, No. 5, pp. 709 – 722, May 2013.

6.        Ke-Ren Dai, Wen-Hao Liu and Yih-Lang Li, " NCTU-GR: Efficient Simulated Evolution Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 20, Issue 3, pp. 459 – 472, Mar. 2012.

7.        Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li, “Critical-Trunk-based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 9, pp. 1335 – 1348, Sep. 2011.

8.        Yih-Lang Li, Yu-Ning Chang, and Wen-Nai Cheng, “A Gridless Routing System with Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track Assignment”, ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol 16, No. 2, Article 19 (1-25), March 2011.

9.        Ying-Zhih Chuang, De-Shiun Fu and Yih-Lang Li, “Enhanced Edge-Based Device Migration under Topology Constraints,” International Journal of Electrical Engineering (IJEE), Vol. 16, No. 6, pp. 493–502, Dec. 2009.

10.     Peng-Yang Hung, Ying-Shu Lou and Yih-Lang Li, “Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E92-A, No.3, pp. 880-889, Mar. 2009.

11.      Yiming Li, Shao-Ming Yu and Yih-Lang Li, “Intelligent Optical Proximity Correction Using Genetic Algorithm with Model- and Rule-based Approaches,” Computational Materials Science, Volume 45, Issue 1, pp. 65-76, Mar. 2009.

12.     Yiming Li, Yih-Lang Li, and Shao-Ming Yu, “Design optimization of a current mirror amplifier integrated circuit using a computational statistics technique,” Mathematics and Computers in Simulation, Vol. 79, Issue 4, 15, pp. 1165-1177, Dec. 2008.

13.     Yiming Li, Shao-Ming Yu and Yih-Lang Li, “Electronic design automation using a unified optimization framework,” Mathematics and Computers in Simulation, Vol. 79, Issue 4, 15, pp. 1137-1152, Dec. 2008.

14.     Yiming Li, Shao-Ming Yu and Yih-Lang Li, “Parallel Solution of Large-Scale Eigenvalue Problem for Master Equation in Protein Folding Dynamics,” Journal of Parallel and Distributed Computing, Vol. 68, Issue 5, pp. 678-685, 2008.

15.     Yih-Lang Li, Xin-Yu Chen, and Zhi-Da Lin, “NEMO: A New Implicit Connection Graph-based Gridless Router with Multi-layer Planes and Pseudo-tile Propagation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 4, pp. 705–718, Apr. 2007.

16.     Yih-Lang Li, Jin-Yih Li and Wen-Bin Chen, “An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 2, pp. 345-358, Feb., 2007. (榮獲臺灣積體電路設計學會(TICD)沈文仁教授紀念獎的年度論文獎(95年))

17.     Yih-Lang Li and Ying-Chao Lai and Cheng-Wen Wu, "VLSI Design of a Cellular-Automata Based Logic and Fault Emulator," Proceedings of the National Science Council, Part A: Physical Science and Engineering, Vol. 21, No. 3, pp. 189-199, May, 1997.

18.     Yih-Lang Li and Cheng-Wen Wu, "Cellular Automata for Efficient Parallel Logic and Fault Simulation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 14, No. 6, pp. 740-749, Jun., 1995.

 

 

(B) Conference Papers

1.        Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, and Hidetoshi Onodera, “MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2020), Virtual, Nov., 2020.

2.        Tai-Cheng Lee, Cheng-Yen Yang, and Yih-Lang Li, “iTPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2020), Virtual, Nov., 2020.

3.        Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo,“DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2020), Virtual, Nov., 2020.

4.        Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo, “DATC RDF-2019: Towards a Complete Academic Reference Design Flow”, ACM/IEEE International Conference on Computer-Aided Design (ICCAD-2019), Denver, Nov, 2019.

5.        Shih-Ting Lin, Hong-Yan Su, Oscar Chen, Yih-Lang Li, “An Efficient Character Generation Algorithm for High-Throughput E-Beam Lithography”, the 22nd Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2019), Tainan, Oct, 2019.

6.        Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, and Hidetoshi Onodera, "NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map", Proceedings of the 30th VLSI Design/CAD Symposium (Best paper award), Kaoshiung, Aug, 2019.

7.        Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, and Hidetoshi Onodera, "NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map", IEEE/ACM Design Automation Conference (DAC-2019), Las Vegas, June, 2019.

8.        Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor Kravets, Gi-Joon Nam, “DATC RDF: An Academic Flow From Logic Synthesis to Detailed Routing”, ACM/IEEE International Conference on Computer-Aided Design (ICCAD-2018) and Workshop on Open-Source EDA Technology (WOSET-2018), San Diego, CA, Nov, 2018.

9.        Shih-Ting Lin, Hong-Yan Su, Oscar Chen, Yih-Lang Li, “An Efficient Character Generation Algorithm for High-Throughput E-Beam Lithography”, ACM/IEEE Design Automation Conference (DAC-2018) (WIP), San Francisco, CA, June, 2018.

10.     Ying-Chi Wei, Radhamanjari Samanta and Yih-Lang Li, “LESAR: A Dynamic Line-End Spacing Aware Detailed Router”, ACM/IEEE Design, Automation and Test in Europe (DATE-2018), Dresden, German, 2018.

11.      Kuen-Wey Lin, Masanori Hashimoto, Yih-Lang Li, “Near-Future Traffic Evaluation based Navigation for Automated Driving Vehicles Considering Traffic Uncertainties”, IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2018.

12.     Jinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Karimpour Darav, Iris Hui-Ru Jiang, Victor N. Kravets, Laleh Behjat, Yih-Lang Li, Gi-Joon Nam, "DATC RDF: Robust Design Flow Database", in Proc. ACM/IEEE International Conference on Computer-Aided Design (ICCAD-2017), Irvine, CA, Nov, 2017.

13.     Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera, "Pin Accessibility Evaluating Model for Improving Routability of VLSI Designs", in Proc. 30th IEEE International System-on-Chip Conference (SOCC-2017), Munich, Germany, September 5-8, 2017.

14.     K.-W. Lin, Y.-S. Lin, Y.-L. Li and R.-B. Lin, "A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points," in Proc. ACM Great Lakes Symposium on VLSI (GLVLSI-2017), Banff, Alberta, Canada, May 10-12, 2017.

15.     K.-W. Lin, Y.-L. Li and M. Hashimoto, "Near-Future Traffic Evaluation based Navigation for Automated Driving Vehicles," in Proc. IEEE Intelligent Vehicles Symposium (IVS-2017), Redondo Beach, California, USA, June 11-14, 2017.

16.     Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, Yih-Lang Li, “OpenDesign Flow Database: The Infrastructure for VLSI Design and Design Automation Research” , ACM/IEEE International Conference on Computer-Aided Design (ICCAD-2016), Austin, TX, Nov, 2016.

17.     Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin, Wen-Hao Liu, “Performance-Driven Multi-Layer OARST Construction with Steiner-Point Pre-Selection and Bounded Maze Routing”, The 20th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016), 2016.

18.     Hong-Yan Su, Bo-Shung Wang, Sin-Ye Hsieh, Yih-Lang Li, I-Hsun Wu, Chang-Chung Wu, Wei-Chiang Shih, Hidetoshi Onodera, Masanori Hashimoto, “Efficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths”, The 20th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016), Kyoto Japan, Oct. 2016. (IEEE CEDA Young Researcher Award)

19.     Kuen-Wey Lin, Yih-Lang Li, Rung-Bin Lin, “Multiple-Patterning Lithography-Aware Routing for Standard Cell Layout Synthesis”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2016), Jeju South Korea, Oct. 2016.

20.    Hong-Yan Su, Chih-Hao Hsu and Yih-Lang Li, “SubHunter: A High-Performance and Scalable Sub-Circuit Recognition Method with Prüfer-Encoding”, Design, Automation and Test in Europe (DATE-2015), Grenoble, France, Mar. 2015.

21.     Hsuesh-Ling Yu, Yih-Lang Li, Tzu-Yi Liao, Tianchen Wang, Yiyu Shi, and Shu-Fei Tsai,"Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated Circuits,"  to appear in ACM/IEEE International Conference on Computer-Aided Design (ICCAD-2014), San Jose, CA, 2014.

22.    Sergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, Ting-Chi Wang, "Density-aware Detailed Placement with Instant Legalization", ACM/IEEE Design Automation Conference (DAC-2014), San Francisco, CA, Jun 2014.

23.    Chih-Chien Lin, Wen-Hao Liu, and Yih-Lang Li, “Skillfully Diminishing Antenna Effect in Layer Assignment Stage”, IEEE International Symposium on VLSI Design, Automation and Test (VLSI DAT 2014), HsinChu, Taiwan, Apr 2014.

24.    Hong-Yan Su, Chieh-Chu Chen, Yih-Lang-Li, An-Chun Tu, Chuh-Jen Wu, Chen-Ming Huang, “A Novel Fast And Accurate Hot Spot Detection Method with Prüfer Code Layout Encoding”, Proceedings of the 24th VLSI Design/CAD Symposium, Kaoshiung, Aug. 2013 (*** Best paper award ***).

25.    Hong-Yan Su, Chieh-Chu Chen, Yih-Lang-Li, An-Chun Tu, Chuh-Jen Wu, Chen-Ming Huang, “A Novel Fast And Accurate Hot Spot Detection Method with Prüfer Code Layout Encoding”, Proceedings of the 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013), Hokkaido, Japan, Oct. 2013 (*** Best paper award ***).

26.    Wen-Hao Liu, Cheng-Kok Koh and Yih-Lang Li, “Optimization of Placement Solutions for Routability”, ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, June 2013.

27.    Wen-Hao Liu, Yaoguang Wei, Cliff, Sze, Charles Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan, “Routing Congestion Estimation with Real Design Constraints”, ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, June 2013.

28.    Wen-Hao Liu, Cheng-Kok Koh and Yih-Lang Li, “Case Study for Placement Solutions in ISPD11 and DAC12 Routability-Driven Placement Contests”, Proceedings of ACM International Symposium on Physical Design (ISPD-2013), The Ridge Tahoe, Stateline, Nevada, March, 2013.

29.    Yen-Hung Lin, Bei Yu, David Z. Pan and Yih-Lang Li, “TRIAD: A Triple Patterning Lithography Aware Detailed Router”, Proceedings of International Conference on Computer-Aided Design (ICCAD 2012), San Jose, California, 2012.

30.    Wen-Hao Liu, Yih-Lang Li and Cheng-Kok Koh, “A Fast Maze-Free Routing Congestion Estimator with Hybrid Unilateral Monotonic Routing”, Proceedings of International Conference on Computer-Aided Design (ICCAD 2012), San Jose, California, 2012.

31.     Iris Hui-Ru Jiang, Zhuo Li and Yih-Lang Li, “Opening: Introduction to CAD contest at ICCAD 2012: CAD contest”, Proceedings of International Conference on Computer-Aided Design (ICCAD 2012), San Jose, California, 2012.

32.    Wen-Hao Liu and Yih-Lang Li, “Optimizing the antenna area and separators in layer assignment of multi-layer global routing”, Proceedings of ACM International Symposium on Physical Design (ISPD-2012), Napa Valley, California, March, 2012. 

33.    Yen-Hung Lin, Yun-Jian Lo, Jian-Syun Tong, Wen-Hao Liu and Yih-Lang Li, “Topology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization”, Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012), Jan. 2012.

34.    Wen-Hao Liu, Yih-Lang Li and Kai-Yuan Chao, “High-Quality Global Routing for Multiple Dynamic Supply Voltage Designs,” Proceedings of International Conference on Computer-Aided Design (ICCAD 2011), San Jose, California, 2011.

35.    Yen-Hung Lin, Yong-Chan Ban, David Z. Pan and Yih-Lang Li, “DOPPLER: DPL-aware and OPC-friendly Gridless Detailed Routing with Mask Density Balancing,” Proceedings of International Conference on Computer-Aided Design (ICCAD 2011), San Jose, California, 2011.

36.    Wen-Hao Liu and Yih-Lang Li, " Negotiation-Based Layer Assignment for Via Count and Via Overflow Minimization," Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Jan. 2011.

37.    Ke-Ren Dai, Yi-Chun Lin, Yih-Lang Li, “A Novel Zone-Based ILP Track Routing,” Proceedings of the 15th Workshop on Synthesis And System Integration of Mixed Information technologies  (SASIMI2010), Taipei, Oct 2010.

38.    Guan-Hung Chen, Ke-Ren Dai, Yih-Lang Li, “Minimizing Wirelength and Overflow of 3D-IC Global Routing by Signal-TSV Planning,” Proceedings of the 15th Workshop on Synthesis And System Integration of Mixed Information technologies  (SASIMI2010), Taipei, Oct 2010.

39.    Yu-Wei Lee, Yen-Hung Lin, Yih-Lang Li, “Efficient Random-Defect Aware Layer Assignment and Gridless Track Routing,” Proceedings of the 15th Workshop on Synthesis And System Integration of Mixed Information technologies  (SASIMI2010), Taipei, Oct 2010.

40.    Yen-Hung Lin and Yih-Lang Li, “Double Patterning Lithography Aware Gridless Detailed Routing with Innovative Conflict Graph”, Proceedings of ACM/IEEE Design Automation Conference (DAC-2010), Anaheim, CA, June 2010.

41.     Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, and Kai-Yuan Chao, “Multi-Threaded Collision-Aware Global Routing with Bounded-Length Maze Routing”, Proceedings of ACM/IEEE Design Automation Conference (DAC-2010), Anaheim, CA, June 2010.

42.    Chih-Ta Lin, Yen-Hung Lin, Guan-Chan Su, Yih-Lang Li, “Dead Via Minimization by Simultaneous Routing and Redundant Via Insertion”, Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010), Taipei, Jan. 2010.

43.    Wen-Hao Liu, Yih-Lang Li, Hui-chi Chen, “Minimizing Clock Latency Range in Robust Clock Tree Synthesis”, Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010), Taipei, Jan. 2010.

44.    Ke-Ren Dai, Chien-Hung Lu, and Yih-Lang Li, “GRPlacer: Improving Routability and Wire-Length of Global Routing with Circuit Replacement”, Proceedings of International Conference on Computer-Aided Design (ICCAD 2009), San Jose, California, 2009.

45.    De-Shiun Fu, Ying-Zhih Chaung, Yen-Hung Lin, and Yih-Lang Li, “Topology-Driven Cell Layout Migration with Collinear Constraints”, Proceedings of International Conference on Computer Design (ICCD 2009), Squaw Creek, Lake Tahoe, California, 2009

46.    Yen-Hung Lin, Shu-Hsin Chang, and Yih-Lang Li, “Critical-Trunk based Obstacle-Avoiding Rectilinear Steiner Tree Routings for Delay and Slack Optimization”, Proceedings of ACM International Symposium on Physical Design (ISPD-2009), San Diego, California, Mar., 2009.

47.    Chih-Ta Lin and Yih-Lang Li, “Yield Improvement in Gridless Detailed Routing with Redundant Via Insertion”, Proceedings of the 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), Okinawa, Mar. 2009. (**Outstanding paper award**)

48.    Yen-Hung Lin, Shu-Hsin Chang, and Yih-Lang Li, “Slack-Driven Obstacle-Avoiding Rectilinear Steiner Tree Routing”, Proceedings of the 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), Okinawa, Mar. 2009.

49.    Ying-Zhih Chuang, De-Shiun Fu, and Yih-Lang Li, “New Device-Level Technology Retargeting Algorithm with Fixed-Topology Constraints”, Proceedings of the 15th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2009), Okinawa, Mar. 2009.

50.    Ke-Ren Dai, Wen-Hao Liu, and Yih-Lang Li, “Efficient Simulated Evolution Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing”, Proceedings of the 14th Asia and South Pacific Design Automation Conference (ASP-DAC 2009), Yokohama, Jan. 2009 (**Best paper nominee**).

51.     Ying-Zhih Chuang, De-Shiun Fu and Yih-Lang Li, “Enhanced Edge-Based Device Migration under Topology Constraints”, Proceedings of the 19th VLSI Design/CAD Symposium, Kending, Aug. 2008 (**Best paper nominee**).

52.    Peng-Yang Hung, Ying-Shu Lou and Yih-Lang Li, “Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing”, Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED-2008), San Jose, CA, Mar., 2008.

53.    Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin and Wen-Nai Cheng, “Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track Assignment for a Gridless Routing System with Fast Pseudo-Tile Extraction”, Proceedings of ACM International Symposium on Physical Design (ISPD-2008), Portland, Oregon, April 2008.

54.    Wen-Nai Cheng, Yu-Ning Zhang, and Yih-Lang Li, “Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track Assignment”, Proceedings of the 14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2007), Hokkaido, Japan, Oct. 2007.

55.    Ke-Ren Dai, Jyun-Yi Lin, and Yih-Lang Li, “A Simple Yet Efficient Global Router with Mirrored Monotonic Routing and Reduced Multi-Source Multi-Sink Maze Routing”, Proceedings of the 18th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2007.

56.    Wen-Nai Cheng, Yu-Ning Zhang, and Yih-Lang Li, “Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track Assignment”, Proceedings of the 18th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2007.

57.    Xin-Yu Chen, Yih-Lang Li, and Zhi-Da Lin, “NEMO: A New Implicit Connection Graph-based Gridless Router with Multi-layer Planes and Pseudo-tile Propagation”, Proceedings of ACM International Symposium on Physical Design (ISPD-2006), San Jose, CA, April 2006.

58.    Meng-Xin Jiang,  Ying-Shu Luo, Yih-Lang Li, “Minimum-Crosstalk Track Assignment with Efficient Track Utilization”, Proceedings of the 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2006) , Nagoya, Japan, April. 2006.

59.    Xin-Yu Chen and Yih-Lang Li, “An Improved Implicit Connection Graph based ECO Router with Multi-Plane Pseudo-Tile Propagation”, Proceedings of the 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.

60.    Meng-Xin Jiang, Ying-Shu Luo, Yih-Lang Li, and Wen-Bin Chen, “Utilization- And Crosstalk-Driven Track Assignment”, Proceedings of the 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.

61.     Meng-Xin Jiang and Yih-Lang Li, “Efficient Coupling-Driven Track Assignment Algorithms,” Proceedings of International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC 2005), Jeju, Korea, July 2005.

62.    Jin-Yih Li and Yih-Lang Li, "An Efficient Tile-Based ECO Router with Routing Graph Reduction and Enhanced Global Routing Flow," Proceedings of ACM International Symposium on Physical Design (ISPD-2005), San Francisco, CA, April 2005.

63.    Yih Lang Li and Cheng Wen Wu, "Logic and Fault Simulation by Massive Parallelism," Proceedings of NCHC High-Speed Computing Application Workshop, pp. 195-198, 1994.

64.    Yih Lang Li and Cheng Wen Wu, "Logic and Fault Simulation by Cellular Automata," Proceedings of EDAC-ETC-EUROASIC, pp. 552-556, 1994.

65.    Yih Lang Li and Cheng Wen Wu, "Cellular Automata for Efficient Parallel Fault Simulation," Proceedings of Fourth VLSI Design/CAD Workshop, pp. 181-185, 1993.

 

Patent

◆ Jui-Chien Wang, Yih-Lang Li, Rule-Driven Method and System For Editing Physical Integrated Circuit Layouts, U.S. Pat. 6341366, Jan. 22, 2002.

 

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