實模式: 不做任何位址轉換，不開分段也不開分頁。识别 processor 是否处于 real mode 的唯一途径就是判断 CR0.PE 标志位。

• 再论 real mode
• Real mode

非實模式: 開機即處於非實模式。之後依序切入實模式、保護模式，再切回實模式。在此過程中，於保護模式將段限長設成 4GB，再切回實模式。但因為此時段限長已為 4GB，並不符實模式的嚴格定義。非實模式是實模式的變種，並非另一種模式，其目的是用來存取實模式存取不到的位址 (1MB)。

• 理解 unreal mode
• Unreal mode

保護模式: 開啟分段。

• protected mode 机制概述
• Protected mode

• processor 模式的切换

虛擬 (邏輯) 地址 (virtual/logical address) → 線性地址 (linear address) → 物理地址 (physical address)

1. 虛擬地址 (virtual address) → 線性地址 (linear address) 使用段機制 (segment) 進行轉換，段機制無法關閉。一般會將段基址設為零，如此一來，虛擬地址等同線性地址。此種作法稱為平坦內存模型 (Flat memory model)。段機制所做的轉換在實模式 (real mode) 和保護模式下 (protected mode) 有所不同。前者的段暫存器中存的是地址，後者的段暫存器中存的則是用來存取段描述符表的索引。
2. 線性地址 (linear address) → 物理地址 (physical address) 使用頁機制 (paging) 進行轉換，頁機制可被關閉。

段描述符表分為全局描述符表 (global descriptor table) 和局部描述符表 (local descriptor table)。分別簡稱為 GDT 和 LDT。存放 GDT 和 LDT 位址的暫存器分別稱為 GDTR 和 LDTR。描述符的內容會被隱式的快取在段暫存器中不可見的部分。所有任務共享一份 GDT，另外保有自己一份 LDT。LDT 本身為一個段，因此在 GDT 中有相對應的描述符指到該 LDT。

• Real mode
  • 再论 real mode
• Unreal mode
  • Big Real Mode
• Memory Translation and Segmentation
• Chapter 2. Memory Addressing

Segmentation provides a mechanism of isolating individual code, data, and stack modules so that multiple programs (or tasks) can run on the same processor without interfering with one another. Paging provides a mechanism for implementing a conventional demand-paged, virtual-memory system where sections of a program’s execution environment are mapped into physical memory as needed. Paging can also be used to provide isolation between multiple tasks. When operating in protected mode, some form of segmentation must be used. There is no mode bit to disable segmentation. The use of paging, however, is optional.

邏輯地址 (logical address) 分為兩部分: 16 位的段選擇符 (segement selector) 和 32 位的偏移 (offset)。

1. 用段選擇符索引段描述符表，取得段描述符。段選擇符包含: 索引、TI (索引 GDT 或是 LDT) 和 RPL。判定是否有權限存取該段，是取 CPL 和 RPL 中
2. 將段描述符中的段基址和偏移相加，得到線性位址。

段暫存器: CS、DS、ES、FS、GS、SS。

• 分段架構
• segmentation 情景分析（上篇）--- 数据结构
• segmentation 情景分析（下篇）--- protected 机制

• 理解 paging
• page 的保护措施
• X86-64 上的 Linux VM 管理系统

頁表項有底下幾項控制位:

• G:
• D:
• A:
• C:
• W:
• U/S: 決定屬於用戶態或是內核態，用戶態無法存取屬於內核態的頁。
• R/W: 決定是否可寫。
• Present (P): 該頁存在物理內存。

• How do x86 page tables work?
• Four-level page tables
• Paging
• Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1 Chapter 4

Software enables paging by using the MOV to CR0 instruction to set CR0.PG. Before doing so, software should ensure that control register CR3 contains the physical address of the first paging structure that the processor will use for linear-address translation (see Section 4.2) and that structure is initialized as desired.

• 32-bit paging: CR0.PG = 1 and CR4.PAE = 0
• PAE paging: CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LME = 0
• IA-32e paging: CR0.PG = 1, CR4.PAE = 1, and IA32_EFER.LME = 1

• CR0.WP
• CR4.PSE
• CR4.PGE
• CR4.PCIDE
• CR4.SMEP
• IA32_EFER.NXE

The first paging structure used for any translation is located at the physical address in CR3.

• Are page table walks cached?
  • Translation Caching: Skip, Don't Walk (the Page Table)

• Page Global Directory (PGD)
• Page Middle directory (PMD)
• Page Table Entry (PTE)
• Page-Map Level 4 (PML4)
• Page-directory-pointer table (PDPT)
• Physical Address Extension (PAE)
• Page Attribute Table (PAT)
• Memory Type Range Register (MTRR)

• Current Privilege Level (CPL)
• Descriptor Privilege Level (DPL)
• Request Privilege Level (RPL)
• Global Descriptor Table (GDT)

MMX → SSE → AVX

• 1-3.CPU進階技術講解，XD、VT、SSE在幹嘛
• X86 Assembly/SSE

• Intel SSE Tutorial : An Introduction to the SSE Instruction Set
• https://developer.apple.com/hardwaredrivers/ve/sse.html
• Using SSE and SSE2: Misconcepts and Reality
• http://www.formboss.net/blog/2010/10/sse-intrinsics-tutorial/
• http://msdn.microsoft.com/en-us/library/y0dh78ez(v=VS.80).aspx

• 2.3
  • 16 128-bit register (xmm0 - xmm15)
  • Streaming SIMD Extensions
  • PD: Packed Double
  • PS: Packed Single
  • SD: Scalar Double
  • SS: Scalar Single
• x86 instruction listings

• 3.1.1.3 Instruction Column in the Opcode Summary Table
  • r/m32 — A doubleword general-purpose register or memory operand used for instructions whose operandsize attribute is 32 bits. The doubleword general-purpose registers are: EAX, ECX, EDX, EBX, ESP, EBP, ESI,

EDI. The contents of memory are found at the address provided by the effective address computation. Doubleword registers R8D - R15D are available when using REX.R in 64-bit mode

• mm — An MMX register. The 64-bit MMX registers are: MM0 through MM7.
• SSE instructions in a buffer

$ gcc -O2 -ftree-vectorize -msse2 -ftree-vectorizer-verbose=5

• How to vectorize with gcc?
• 3.10 Options That Control Optimization
  • `-ftree-vectorize`
    • Perform loop vectorization on trees. This flag is enabled by default at -O3.
• 3.17.16 Intel 386 and AMD x86-64 Options
  • `-msse2`
    • These switches enable or disable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, BMI, BMI2, LZCNT, RTM or 3DNow! extended instruction sets.
• Using GCC Auto-Vectorizer

$ gcc -mfpu=neon -mfloat-abi=softfp or -mfloat-abi=hard

• Auto-vectorization with gcc 4.7
• Auto vectorization in llvm

• Time Stamp Counter
  • How to Benchmark Code Execution Times on Intel® IA-32 and IA-64 Instruction Set Architectures
  • Using the RDTSC Instruction for Performance Monitoring
  • 多核时代不宜再用 x86 的 RDTSC 指令测试指令周期和时间
• AMD CPU bug 問題…
  • Buildworld loop seg-fault update -- I believe it is hardware
  • AMD cpu bug update -- AMD confirms! (additional info)
• Oral history of Robert P. Colwell (1954- )

• mouseOS 技术小站
• Intel Architecture 保護模式架構
• x86-64 Machine-Level Programming
• Intel® 64 and IA-32 Architectures Software Developer Manuals
• AMD Developer Central