劉文皓 博士, Wen-Hao Liu, Ph. D. Sr. Principal Engineer Cadence Design Systems Austin, TX, USA E-mail: whliu {at} cadence {dot} com

Education

B.S.,	Computer Science, National Chiao Tung University, Taiwan,	2004/09~2008/07.
Ph.D.,	Computer Science, National Chiao Tung University, Taiwan,	2008/09~2013/02.

Experience

Part-time Software engineer	United Microelectronics Corporation (UMC)	2007/06~2008/01
Visiting Scholar	Electrical and Computer Engineering, Purdue University	2012/03~2012/08
Visiting Scholar	IBM Austin Research Lab, TX, USA	2012/08~2012/11
Postdoctoral Research Fellow	Computer Science, National Tsing Hua University	2013/02~2014/01
Sr. Member of Technical Staff	Cadence Design Systems, Austin, TX	2014/01~2015/06
Principal Engineer	Cadence Design Systems, Austin, TX	2015/06~2016/06
Sr. Principal Engineer	Cadence Design Systems, Austin, TX	2016/06~present

Research Interests

Physical Design Automation– Routing, Placement, Clock Network Synthesis

Parallel Computing, GPU Computing

Publication List

IEEE/ACM Journal Papers:

1. Ke-Ren Dai, Wen-Hao Liu and Yih-Lang Li, "NCTU-GR: Efficient Simulated Evolution Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing," IEEE Transactions on Very Large Scale Integration Systems, 2012. (TVLSI)

2. Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, and Kai-Yuan Chao, “NCTU-GR 2.0: Multi-Threaded Collision-Aware Global Routing with Bounded-Length Maze Routing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, accept, 2013. (TCAD)

3. Wen-Hao Liu, and Yih-Lang Li, “Optimizing Antenna Area and Separators in Layer Assignment of Multi-Layer Global Routing,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, accept. (TCAD)

IEEE/ACM Conference Papers:

1. Ke-Ren Dai, Wen-Hao Liu and Yih-Lang Li, "Efficient Simulated Evolution Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing," (ASP-DAC 2009, acceptance rate 33%)

2. Wen-Hao Liu, Yih-Lang Li, Hui-chi Chen, “Minimizing Clock Latency Range in Robust Clock Tree Synthesis,” (ASP-DAC 2010, acceptance rate 35%)

3. Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, and Kai-Yuan Chao, “Multi-Threaded Collision-Aware Global Routing with Bounded-Length Maze Routing,” (DAC 2010, acceptance rate 24%)

4. Wen-Hao Liu and Yih-Lang Li, "Negotiation-Based Layer Assignment for Via Count and Via Overflow Minimization," (ASP-DAC 2011, acceptance rate 35%)

5. Wen-Hao Liu, Yih-Lang Li, and Kai-Yuan Chao, "High-Quality Global Routing for Multiple Dynamic Supply Voltage Designs," (ICCAD 2011, acceptance rate 26%)

6. Yen-Hung Lin, Yun-Jian Lo, Jian-Syun Tong, Wen-Hao Liu and Yih-Lang Li, "Topology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization," (ASP-DAC 2012, acceptance rate 34%)

7. Wen-Hao Liu and Yih-Lang Li, "Optimizing Antenna Area and Separators in Layer Assignment of Multi-Layer Global Routing," (ISPD 2012, acceptance rate 33%)

8. Wen-Hao Liu, Yih-Lang Li and Cheng-Kok Koh, “A Fast Maze-Free Routing Congestion Estimator With Hybrid Unilateral Monotonic Routing,” (ICCAD 2012, acceptance rate 24%)

9. Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li, "Case Study for Placement Solutions in ISPD11 and DAC12 Routability-Driven Placement Contests," (ISPD 2013, acceptance rate 31%)

10. Wen-Hao Liu, Cheng-Kok Koh and Yih-Lang Li, “Optimization of Placement Solutions for Routability,” (DAC 2013, acceptance rate 23%)

11. Wen-Hao Liu, Yaoguang Wei, Cliff Sze, Charles Alpert, Zhuo Li, Yih-Lang Li and Natarajan Viswanathan, “Routing Congestion Estimation with Real Design Constraints,” (DAC 2013, acceptance rate 23%)

12. Wen-Hao Liu, Tzu-Kai Chien and Ting-Chi Wang, "Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost," (DATE 2014, acceptance rate 23.1%)

13. Wen-Hao Liu, Tzu-Kai Chien, and Ting-Chi Wang, "A Study on Unroutable Placement Recognition," (ISPD 2014)

14. Vladimir Yutsis, Ismail Bustany, David Chinnery. Joseph Shinnerl, and Wen-Hao Liu, "ISPD 2014 Benchmarks with Sub-45nm Technology Rules for Detailed Routing Driven Placement," (ISPD 2014)

15. Chih-Chien Lin, Wen-Hao Liu, and Yih-Lang Li, " Skillfully Diminishing Antenna Effect in Layer Assignment Stage," (VLSI-DAT 2014)

16. Wen-Hao Liu, Min-Sheng Chang, and Ting-Chi Wang, "Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs," (DAC 2014)

17. Sergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, and Ting-Chi Wang, "Density-aware Detailed Placement with Instant Legalization," (DAC 2014)

18. Rickard Ewetz, Cheng-Kok Koh, Wen-Hao Liu, Ting-Chi Wang and Kai-Yuan Chao, "A study on the use of parallel wiring techniques for sub-20nm designs," (GLSVLSI 2014)

19. Wen-Hao Liu, Zhen-Yu Peng, and Ting-Chi Wang, " A Resource-level Parallel Approach for Global-routing-based Routing Congestion Estimation and a Method to Quantify Estimation Accuracy," (ICCAD 2014)

20. Man-Pan Wong, Wen-Hao Liu, Ting-Chi Wang, “Negotiation-based track assignment considering local nets” (ASP-DAC 2016)

21. Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan, “MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes” (ICCAD 2016)

22. S. Han, Wen-Hao Liu, R. Ewetz, C.-K Koh, K.-Y Chao, and T.-C Wang, “Delay-driven Layer Assignment for Advanced Technology Nodes”, Asia and South Pacific Design Automation Conference (ASP-DAC 2017)

Other Conference Papers:

1. Wen-Hao Liu, Yih-Lang Li, and Kai-Yuan Chao, “Globally Routing Multiple Dynamic Supply Voltage Designs”, 22st VLSI Design/CAD Symposium, Yunlin, Taiwan, Aug. 2-5, 2011. (VLSI/CAD 2011)

2. Li-Chung Chou, Yen-Hung Lin, Yih-Lang Li and Wen-Hao Liu, "ECO Timing Optimization with Elmore Delay Model," in The 26th International Technical Conference on Circuits/Systems, Computers and Communications, 2011. (ITC-CSCC 2011)

Invited Talk

1. "How to Make Global Routers Faster", IBM Austin Research Lab, Austin, USA, 2012/09/07.

2. "Five Weeks to a New Rough Router", IBM Austin Research Lab, Austin, USA, 2012/10/25.

3. "Routing? Heaven or Hell?", National Taiwan University, Taipei, Taiwan, 2013/05/13.

4. "Optimizing Routability and Performance of Placement and Routing Flow for Nanometer Designs", AtopTech, Taipei, Taiwan, 2013/05/13

5. "Fast Routability Estimation", Ritsumeikan University, Japan, 2013/09/03.

6. "My Exciting PhD journey!", EDA Forum, HsinChu, 2013/10/11.

Software Release

NCTU-GR

NCTU-GR is a unified placement and routing tool that includes the following four utilities.

Regular mode	: a powerful global router to efficiently remove overflows and find shorter routing wirelength
Fast mode	: a fast light global router that can be used in predicting routing congestion in the early stages before routing
Routability optimizer	: a post-placer that reads a placement solution and then do re-placement to improve routability
Format Converter	: translate ISPD11 and DAC12 placement solutions from the academic format to LEF/DEF format

Academic Activities

1. Session Chair of computer aided design session at ITC-CSCC, Korea. (2011)

2. Reviewer of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (2012/02~prsent)

3. Reviewer of ACM Transactions on Design Automation of Electronic Systems. (2013/04~prsent)

4. Reviewer of IEEE Transactions on Very Large Scale Integration Systems. (2013/05~prsent)

5. Reviewer of Integration, the VLSI Journal. (2013/08~prsent)

6. Technical Program Committees, IEEE/ACM 19th Asia and South Pacific Design Automation Conference. (2013/05~2014/02)

7. Best Paper Selection Committees, IEEE/ACM 19th Asia and South Pacific Design Automation Conference. (2013/09~2014/02)

8. Co-organizer, ACM SIGDA Cadathlon Contest. (2013/10~2013/11)

9. Co-organizer, ISPD 2014 physical design contest. (2013/08~2014/04)

10. Technical Program Committees, IEEE/ACM International Symposium on Physical Design. (2016/10~present)

11. Technical Program Committees, IEEE/ACM Design Automation Conference. (2017/02~present)

Honors and Awards

Contest

1. The Sixth Place of ISPD Global Routing Contest, 2008.

2. The First Place of the Project Contest of Computer Science Department, National Chiao Tung University, 2008 (Topic: 3D rectilinear steiner minimal tree construction)

3. National Contestant, Domestic CADathlon Competition, Ministry of Education, Taiwan, 2008.

4. The winner of ISPD Clock Network Synthesis Contest, 2009.

5. Director of the team to win the first place in the IC/CAD Taiwan domestic contest on mask optimization topic, 2013.

6. Director of the team to win the first place in the IC/CAD Taiwan domestic contest on detailed placement topic, 2013.

Scholarship

1. Algorithm Outstanding Scholarship of Computer Science Department, National Chiao Tung University, 2007.

2. SpringSoft EDA Scholarship for ISPD clock contest, 2009.

3. Synopsys Scholarship for EDA Ph.D Student in Taiwan, 2009.

4. SpringSoft EDA Scholarship for DAC regular paper, 2010.

5. EDA Workshop Scholarship for outstanding research paper, 2011.

6. EDA Workshop Scholarship for outstanding research paper, 2012.

7. EDA Workshop Scholarship for outstanding research paper, 2013.

Other

1. Best Paper Nominee, IEEE/ACM ASP-DAC, 2009.

2. NCTU-GR was selected to be the evaluation tool used in the DAC12 and ICCAD12 placement contests, 2012.

3. Honorary Member, the Phi Tau Phi Scholastic Honor Society, 2013.