6. Virtual memory
   - address space
     - What is the address space?
	- The running program's view of memory
	- e.g. program code (0 - 1KB) where instruction live
	- e.g. heap (1KB -> ) contains malloc() data
	- e.g. stack (bottom of the address space ->) includes
	  - local variables, arguments to routines, return values 
     - address space on uni-programming (DOS)
	- one process at a time
	- OS sits in a fixed range of address space, e.g. above 640 KB
	- No hardware virtualization of address
	- Safety: None, non-overlapping on I/O and compute
     - address on multi-programming (static relocation)
	- What is the static relocation ?
	  - Moving data or codes to absolute locations before running a program
	  - Advantage
	    - without the support of the hardware. why?
	  - Problem
	    - creating contiguous holes
     - dynamic relocation
	- relocate addresses when used
	- program-generated address is translated to hardware address
	- virtual address: the view of each process
	- physical address: the view of the hardware
	- rely on MMU (memory management unit) hardware
	- variants: base and bounds, segmentation, paging
     - base and bounds (see slide 13)
	- two hardware registers
	  - base: staring physical address
	  - bounds: size in bytes (block size)
	- physical address = virtual address + base
	- pros
	  - efficient -> only a little hardware logic is required
	  - isolation (protection), why?
	    - no process can generate memory reference outside its own address space
	- cons
	  - fragmentation, why? 
	    - contiguous memory space for each process
	    - what kinds of fragmentation shown in relocated process?
	      - restrict to place an address space in a fixed-sized slot
	    - How to avoid this fragmentation?
	  - No sharing
	    - cannot share limited parts of address space
   - segmentation
     - create N separate segments for a process. why?
     - each segment has separate base and bounds register
     - a segment
	- a contiguous portion of the address space with a particular length
     - how does the segmentation work? (see slide 20)
	- check if the address is within bounds at every reference
     - segmented address translation (see slide 25)
	- SN (segment number) 
	  - used to indicate specified segments 
	- SO (segment offset)
	  - segment size
	  - segments can have different sizes
	- segment translation
	  - maps SN to corresponding base and bonud
	  - spearate mapping for each process
     - global descriptor table (GDT) or segment table
	- preserve each segment descriptor
	  - What is inside the segment descriptor? (see slide 27)
	    - base (32 bit)
	    - descriptor privilege level (DPL) 0 - 3: (DPL_USER: 3, kernel: 0)
	    - segment limit (20 bit)
	    - descriptor type (0: system, 1: code or data ...
	- store in the memory
	- GDT register (GDTR) is used to point to the entry of the GDT
	  - lgdt -> instruction used to load the GDT register
      - what is segmentation fault ?
	- beyond the end of heap (out of bound)
	- traps into the OS and terminates the offending process
      - which segment an address refers? (see slide 29)
	- translate virtual address in the binary form
	- the top two bit tells the hardware which segment we are referring to
	  - two bits to represent three segments (code, heap, and stack)
	- the other bits are offset into the segment
      - support for sharing (see slide 33)
	- share certain memory segments between address space
	- need protection bits per segment
	- the read-only segment can be shared across multiple processes
      - pros
	- reduces severity of fragmentation (how?)
	- more flexible than base and bounds -> enable sharing (how?)
      - cons
	- Still have fragmentation (which one?)
	  - variable-sized segments
  	- How to resolve this fragmentation? (paging)
   - virtual memory
     - problems of physical memory addressing
	- physical memory is of limited size
	- inconvenient for programmers to management
	- protection and isolation between processes
     - illusion of a large address space while having a small physical memory
     - only a portion of the virtual address space lives in the physical address space
     - require both HW + SW support
	- TLB (translation lookaside buffers)
     - page based address translation
	- 4GB virtual memory, 1GB physical memory, page size is 4KB (2^12) with 
          2^18 physical pages (See slide 9, 10)
     - page table
	- stores the mapping of virtual pages to physical frames
	- page table is in the memory
     - paging
	- All chunks (pages) be the same size (512 bytes - 8KB)
	- Allocation is done in terms of full page-aligned pages -> no bounds
	- MMU maps virtual page numbers to physical page numbers
	- page table is per process
	  - each process has its own virtual address space
	  - each process has a separate page table
	  - a page table register points to the current process's page table
	- page table (see slide 17)
	  - indexed with the virtual page number (VPN)
	  - each entry contains a valid bit and physical page number (PPN)
	  - if valid = 0, then page not memory (page fault)
	- page hit and page fault (see slide 20, 21)
	- pros
	  - No external fragmentation
	  - easy translation because everything aligned on power-of-2 addresses
	  - easy for OS to manage/allocate free memory pool
	- cons
	  - page table may be large
	  - slow paging 
	- What is inside a page table entry (PTE)? (see slide 22)
	  - present bit, protection, dirty, reference bit ...
	- slow paging
	  - paging logically requires an extra memory lookup for each virtual address
	  - going to memory for translation information before every instruction fetches
	  - explicit load or store is slow
	- translation lookaside buffer (TLB) (See slide 24)
	  - reduce memory reference time
	  - a hardware cache of popular virtual-to-physical address translation
	  - caching of the page table
	  - few entries (16 - 512)
	  - fully associative (why?)
	- TLB entry
	  - dirty, coherence, valid, address space identifier (ASID) that keeps process id
	- overlap the cache access and TLB access
	  - high order bits of the VA are used to look in the TLB
	  - low order bits of the VA are used as index into cache
	- virtual physical cache (see slide 33)
	  - indexed by VAs
	  - tagged by PAs
	  - cache access and address translation in parallal
	- handling TLB misses
	  - must access memory to find the appropriate PTE
	  - hardware-managed
	    - the hardware does the page walk
	    - the hardware fetches the PTE and inserts it into the TLB
	  - software-managed
	    - the hardware raises an exception
	    - the OS does the page walk, and fetches the PTE