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Description: C:\Documents and Settings\Administrator\My Documents\WCHsu\flowertest.gifPUBLICATIONS

Book Chapter

Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Compilation and Speculation, Chapter 12 in Speculative Execution in High Performance Computer Architectures, http://www.ece.neu.edu/groups/nucar/CRCBook/, 2004

Refereed Journal Publications

1) Yangchun Luo, Venkatesan Packirisamy, Wei Chung Hsu, and  Antonia Zhai, "Dynamically Dispatching Speculative Threads to Improve Sequential Execution”,  ACM Transaction on Architecture and Code Optimization  (TACO),  accepted to appear.

2) Jianjun Li, Chenggang Wu and Wei Chung Hsu, "Efficient and Effective Misaligned Data Access Handling in a Dynamic Binary Translation System”, ACM Transaction on Architecture and Code Optimization  (TACO),  June, 2011.

3) Vineeth Mekkat, Ragavendra Natarajan, Wei Chung Hsu, and Antonia Zhai, “Effectiveness of Compiler Directed Prefetching on Data Mining Benchmarks”, 1 Special Issue on Interaction between Compilers and computer Architectures, accepted to appear at IEEE Journal of Circuites, Systems and Computers.

4) Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Douglas Hawkins, Wei-Chung Hsu, Pen-Chung Yew, " CIM: A Reliable Metric for Evaluating Program Phase Classifications", IEEE Computer Architecture Letters, vol. 6, no. 1, Jan-Jun, 2007.

5) Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Ju, and T. Ngai, "Recovery Code Generation for General Speculative Optimizations", ACM Transcation on Architecture and Code Optimization (TACO), Volume 3, Issue 1, March, 2006.

6) Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan, "A compiler framework for speculative optimizations", ACM Transactions on Architecture and Code Optimization (TACO), Volume 1, Issue 3, September 2004

7) Jiwei Lu, Howard Chen, Pen-Chung Yew, Wei Chung Hsu, "Design and Implementation of a Lightweight Dynamic Optimization System" in the Journal of Instruction-Level Parallelism, (JILP), Volume 6, 2004

8) Wei Hsu and Jim Smith, " A Performance Study of Instruction Cache Prefetching Methods", IEEE Transaction on Computers, (TOC), May, 1998.

9) Steven P. Vander Wiel, David J. Lilja and Wei Hsu, "When Caches Aren't Enough: Data Prefetching Techniques", Side Bar Contribution, IEEE Computer, July, 1997, Volume 30.

10) Sriram Vayapeyam and Wei Hsu, "Towards Efficient Scalar Hardware for Highly Vectorizable Applications", Journal of Parallel and Distributed Systems, Special issue on performance of supercomputers. Oct., 1993.

11) Guri Sohi and Wei Chung Hsu, "The Use of Intermediate Memories for Low-Latency Memory Access in Supercomputer Scalar Units", the Journal of Supercomputing, 4, 1990.

12) Wei Chung Hsu, C. Fischer and J. Goodman, "On the Minimization of Loads/Stores in Local Register Allocation", IEEE Transactions on Software Engineering, Oct. 1989.


Highly Competitive Conference Publications

13) Ding-Yong Hong, Jan-Jan Wu, Wei-Chung Hsu, Pen-Chung Yew,” HQEMU: A Multi-Threaded and Retargetable Dynamic Binary Translator on Multicores”, to appear at the Tenth Annual IEEE/ACM International Symposium on Code Generation and Optimization, (CGO-2012), Apr. 2012.

14) Jiun-Hung Ding,  Po-Chun Chang,  Wei-Chung Hsu,  Yeh-Ching Chung, “PQEMU: A Parallel System Emulator Based on QEMU”,IEEE International Conference on Parallel and Distributed Systems,  ICPADS 2011, Dec., 2011 (best paper award)

15) Chih-Sheng Wang, Yeh-Ching Chung, Wei-Chung Hsu, Wei-Kuan Shih, Hong-Rong Hsu and Chih-Ying Wu  “A Method-Based Ahead-of-Time Compiler for Android Applications”, International Conference on Compilers Architectures and Synthesis of Embedded Systems, CASES 2011, Oct. 2011

16) Chun-Chen Hsu, Pangfeng Liu, Chien-Min Wang, Jan-Jan Wu, Ding-Yong
Hong, Pen-Chung Yew and Wei-Chung Hsu, “LnQ: Building High Performance Dynamic Binary Translators with Existing Compiler Backends”,  The 2011 International Conference on Parallel Processing (ICPP2011), Sept., 2011.

17) Jianjun Li, Chenggang Wu and Wei Chung Hsu, “Dynamic Register Promotion of Stack Variables”, Proceedings of the Ninth Annual IEEE/ACM International Symposium on Code Generation and Optimization, (CGO-2011), Apr. 2011.

18) Yangchun Luo, Venkatesan Packirisamy Wei-Chung Hsu, A. Zhai, “Energy Efficient Speculative Threads: Dynamic Thread Allocation in Same-ISA Heterogeneous Multicore Systems”, The Nineteenth International Conference on Parallel Architectures and Compilation Techniques, (PACT 2010), Sept. 2010

19) Yangchun Luo, Venkatesan Packirisamy, Nikhil Mungre, Ankit Tarkas, Antonia Zhai, and Wei Chung Hsu, “Dynamic Performance Tuning for Speculative Threads”, Proceedings of the International Symposium on Computer Architecture, (ISCA'09), June, 2009.

20) Jianjun Li, Chenggang Wu and Wei Chung Hsu, “An Evaluation of Misaligned Data Access Handling Mechanisms in Dynamic Binary Translation Systems”, Proceedings of the Seventh Annual IEEE/ACM International Symposium on Code Generation and Optimization, (CGO-2009), March 2009.

21) Venkatesan Packirisamy, Antonia Zhai, Pen Chung Yew, and Wei Chung Hsu, “ Exploring Speculative Parallelism in SPEC2006”, International Symposium on Performance Analysis of Systems and Software, ISPASS-2009, Apr., 2009

22) Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Wei-Chung Hsu, Pen-Chung Yew, " Analysis of Statistical Sampling in Microarchitecture Simulation: Metric, Methodology and Program Characterization”, 2007 IEEE International Symposium on Workload Characterization, September 2007.

23) Jinpyo Kim, Wei-Chung Hsu, Pen-Chung Yew, " COBRA: An Adaptive Runtime Binary Optimization Framework for Multithreaded Applications", The 2007 International Conference on Parallel Processing (ICPP-07), September 2007.

24) Venkatesan Packirisamy, Shengyue Wang, Antonia Zhai, Wei-Chung Hsu and Pen-Chung Yew, "Supporting Speculative Multithreading on Simultaneous Multithreaded Processors", 13th Annual IEEE International Conference on High Performance Computing (HiPC 2006), December, 2006(acceptance rate: 16%)

25) Abhinav Das, Jiwei Lu, Wei-Chung Hsu, "Region Monitoring for Local Phase Detection in Dynamic Optimization Systems", Proceedings of the Fourth Annual IEEE/ACM International Symposium on Code Generation and Optimization, (CGO-2006), March 2006. (acceptance rate 30%)

26) Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Ngyuan, Santosh Abraham, "Dynamic Helper Threaded Prefetching on the SUN Ultra SPARC CMP Processor", in Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture, (Micro-38) , 2005(acceptance rate: 15%)

27) Jimpyo Kim, Sreekumar Kodakara, Wei-Chung Hsu, David Lilja and Pen-Chung Yew, "Dynamic Code Region (DCR)-based Program Phase Tracking and Prediction for Dynamic Optimizations" in Proceedings of the First High Performance Embedded Architecture and Compilers, HiPEAC2005, 2005.
(acceptance rate 18%)

28) Abhinav Das, Jiwei Lu, Howard Chen, JinPyo Kim, Wei-Chung Hsu, Pen-Chung Yew, and Dong-Yuen Chen "Performance of Runtime Optimization on BLAST" 2005 International Symposium on Code Generation and Optimization (CGO-2005), March 20-25, San Jose, 2005
(acceptance rate: 30%)

29) Xiao Dai, Wei-Chung Hsu, Antonia Zhai, Pen-Chung Yew, "A General Compiler Framework for Speculative Optimization Using Data Speculative Code Motion" 2005 International Symposium on Code Generation and Optimization (CGO-2005), March 20-25, San Jose, 2005
(acceptance rate: 30%)

30) Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook. Ngai "A Compiler Framework for Recovery Code Generation in General Speculative Optimizations" In Proceedings of International Conference on Parallel Architectures and Compilation Techniques (PACT), Oct, 2004

31) Tong Chen, Jin Lin, Wei Hsu, Pen-Chung Yew, "Data Dependence Profiling for Speculative Optimizations" Proceedings of the 13th International Conference on Compiler Construction (CC), March, Barcelona, Spain, 2004.

32) Jiwei Lu, Howard Chen, Rao Fu, Wei Hsu, Pen-Chung Yew, D. Chen "The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System" in Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, (Micro-36), San Diego, California, Dec. 3-5, 2003,(acceptance rate 15%)

33) Jin Lin,Tong Chen,Wei Hsu,Pen-Chung Yew,Roy Ju "A Compiler Framework for Speculative Analysis and Optimizations" In Proceedings of the SIGPLAN'03 Conference on Programming Language Design and Implementation (PLDI-2003), June, 2003(acceptance rate 15%)

34) Howard Chen,Wei-Chung Hsu,Jiwei Lu,Pen-Chung Yew,Dong-Yuan Chen "Dynamic Trace Selection Using Performance Monitoring Hardware Sampling" Proceedings of 1st Annual IEEE/ACM International Symposium on Code Generation and Optimization, (CGO-2003), March, 2003 (acceptance rate 30%)

35) Jin Lin,Tong Chen,Wei-Chung Hsu and Pen-Chung Yew "Speculative Register Promotion Using Advanced Load Address Table (ALAT)" Proceedings of First Annual IEEE/ACM International Symposium on Code Generation and Optimization, (CGO-2003), March, 2003(acceptance rate 30%)

36) Vatsa Santhenam, Eddie Gornish, and Wei Hsu, "Data Prefetch in the HP-PA8000", Proceedings of the International Symposium on Computer Architecture, (ISCA'97), June, 1997. (acceptance rate 15%, paper cited 67 times)

37) Dave Dunn and Wei Hsu, "Instruction Scheduling for the HP-PA8000", Proceedings of the 29th Annual International Symposium on MicroArchitecture, (Micro-29), Dec., 1996.
(acceptance rate 20%)

38) Wei Hsu and Jim Smith, "Performance of Cached DRAM in Vector Supercomputers", Proceedings of the International Symposium on Computer Architecture (ISCA'93), 1993.(acceptance rate 15%)

39) Sriram Vayapeyam and Wei Hsu, "On the Instruction-Level Characteristics of Inherently Scalar Code in Highly-Vectorized Scientific Applications", Proceedings of the 25th Annual International Symposium on MicroArchitecture, (Micro-25), 1992.(acceptance rate 20%)

40) Jim Smith and Wei Hsu, "Prefetching in Supercomputer Instruction Caches"Supercomputing, (SC'92), Nov., 1992.

41) Sriram Vajapeyam, Wei Hsu and Guri Sohi, "An Empirical Study of the Cray Y-MP processor using the Perfect Club Benchmarks", Proceedings of the International Symposium on Computer Architecture, (ISCA'91), 1991. (acceptance rate 15%)

42) Jim Smith, Wei Chung Hsu and C. Hsiung, "Future General Purpose Supercomputer Architecture", Supercomputing, (SC'90), 1990.

43) Sriram Vajapeyam, Guri Sohi, and Wei Chung Hsu, "Exploitation of Instruction-Level Parallelism in a Cray X-MP processor", Proceedings of the International Conference on Computer Design, (ICCD'90), 1990

44) J. Goodman and Wei Chung Hsu, "Code Scheduling and Register Allocation in Large Basic Blocks" the International Conference on Supercomputing, International Conference on Supercomputing, (ICS'88), 1988. (paper cited 216 times)

45) A. Pleszkun, J. Goodman, Wei Chung Hsu, ate. al., "WISQ: A Restartable Architecture Using Queues" Proceedings of the International Symposium on Computer Architectures, (ISCA'87), 1987.

46) J. Goodman and Wei Chung Hsu, "On the Use of Registers vs. Cache to Minimize Memory Traffic", Proceedings of the International Symposium on Computer Architectures, (ISCA'86), 1986

Refereed Conference Publications

47)  Chun-Chen Hsu, Pangfeng Liu, Chien-Min Wang, Jan-Jan Wu, Ding-Yong Hong, Pen-Chung Yew, and Wei-Chung Hsu  “LnQ: Building High Performance Dynamic Binary Translators with Existing Compiler Backends”, Workshop on Compiler Techniques for High Performance and Embedded Computing, CTHPC-11, June, 2011

48)  Chih-Sheng Wang, Yeh-Ching Chung, Wei-Chung Hsu, Wei-Kuan Shih, Hong-Rong Hsu, Chih-Ying Wu, “A Method-Based Ahead-of-Time Compiler for Android Applications”, Workshop on Compiler Techniques for High Performance and Embedded Computing, CTHPC-11, June, 2011.

49)  Jiun-Hung Ding,  Po-Chun Chang,  Wei-Chung Hsu,  Yeh-Ching Chung, “A Parallel Dynamic
Binary Translation Design for Multi-core System Emulator", Workshop on Compiler Techniques for High Performance and Embedded Computing, CTHPC-11, June, 2011.

50)  Jiun-Hung Ding,  Shih-Wei Li,  Wei-Chung Hsu,  Yeh-Ching Chung, “ARMvisor: System
Virtualization for ARM”, Workshop on Compiler Techniques for High Performance and Embedded Computing, CTHPC-11, June, 2011

51)  Bor-Yeh Shen, Wei Chung Hsu, and Wuu Yang, "Register Reassignment for Mixed-Width ISAs is an NP-Complete Problem," Proceedings of the International Multi-Conference on Complexity, Informatics and Cybernetics (IMCIC 2010), pp. 139-143, Orlando, Florida, USA, Apr. 6-9, 2010.

52)  Shuai-Wei Huang, Yu-Sheng Chen, Jean Jyh-Jiun Shann, Wei-Chung Hsu, Wuu Yang, "A New Approach for Improving Ported Java JIT Compilers for Embedded Systems," in Proceedings of the 2008 International Computer Symposium (ICS'08), Volume 1, pp. 299-304, Taipei, Taiwan, Nov., 2008.

53)  Vineeth Mekkat, Ragavendra Natarajan, Wei hung Hsu, and Antonia Zhai, “Performance characterization of data mining benchmarks”, Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture, INTERACT 14, held with ASPLOS 2010.

54)   Jyh-Shian Wang, I-Wei Wu, Yu-Sheng Chen, Jean Jyh-Jiun Shann, Wuu Yang, Wei-Chung Hsu “Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor”, 2009 International Conference on Computational Science and Engineering, Vancouver, Canada, Aug. 2009

55)  Shuai-Wei Huang, Yu-Sheng Chen, Jean Jyh-Jiun Shann, Wei-Chung Hsu, Wuu Yang “A New Approach for Improving Ported Java JIT Compilers for Embedded Systems”, 2008 International Computer Symposium, Tamsui, Taiwan, 2008

56)  Tzu-Han Hung, Jiunn-Yeu Chen, Wuu Yang, and Wei Chung Hsu, “Program Type Recognition for Compiler Optimizations”, ODES-7 (7th Workshop on Optimizations for DSP and Embedded Systems, held with CGO2009), 2009.

57)  Jiunn-Yeu Chen, Wuu Yang, Jack Hung, Charlie Su and Wei Chung Hsu, “A Static Binary Translator for Efficient Migration of ARM based Applications”, ODES-6 (6th Workshop on Optimizations for DSP and Embedded Systems, held with CGO2008), 2008.

58)  Jinpyo Kim, Wei-Chung Hsu, Pen-Chung Yew, Sreekumar R. Nair, Robert Y. Geva, " Entropy-based Profile Characterization and Classification for Automatic Profile Management", The 12th Asia-Pacific Computer Systems Architecture Conference, August 2007.

59)  Peng-fei Chuang, Howard Chen, Gerolf F. Hoflehner, Daniel M. Lavery, and Wei-Chung Hsu, "Dynamic Profile Driven Code Version Selection", The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture, 2007.

60)  Rao Fu, Antonia Zhai, Pen-Chung Yew and Wei-Chung Hsu, Jiwei Lu, " Reducing Queuing Stalls Caused By Data Prefetching", The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture, 2007.

61)  Rao Fu, Jiwei Lu, Anotonia Zhai, and Wei-Chung Hsu, "A Study of the Performance Potential for Dynamic Instruction Hints Selection", 11th Asia-Pacific Computer Systems Architecture Conference (ACSAC 2006), September 6-8, 2006.(Also published in "Advances in Computer Systems Architecture", Lecture Notes in Computer Science , Vol. 4186, Springer, ISBN: 3-540-40056-7)

62)  Abhinav Das, Anotonia Zhai, Rao Fu, and Wei-Chung Hsu, "Issues and Support for Dynamic Register Allocation", 11th Asia-Pacific Computer Systems Architecture Conference (ACSAC 2006), September 6-8, 2006 (Also published in "Advances in Computer Systems Architecture", Lecture Notes in Computer Science , Vol., 4186, Springer, ISBN: 3-540-40056-7)

63)  Howard Chen, Jiwei Lu, Wei-Chung Hsu, Pen-Chung Yew "Continuous Adaptive Object-Code Re-optimization Framework" Ninth Asia-Pacific Computer Systems Architecture Conference (ACSAC-2004), pp. 241 - 255, Sep., 2004 (acceptance rate: 30%)

64)   Jin Lin, Tong Chen, Wei Hsu, Pen-Chung Yew, "On Speculative Optimizations Using Alias Profiling and Heuristics for C Programs ", EPIC-3 Workshop, held with CGO-2004, March, 2004 (acceptance rate: 30%)

65)  Tong Chen,Jin Lin, Wei Hsu, Pen-Chung Yew, "An Empirical Study on the Granularity of Pointer Analysis in C Programs", Proceedings of 15th Workshop on Languages and Compilers for Parallel Computing (LCPC'02), July, 2002.

66)  Tong Chen, Jin Lin, Wei C. Hsu, Pen Yew, "On the Impact of Naming Methods for Heap-Oriented Pointers in C Programs", The Sixth International Symposium on Parallel Architectures, Algorithms,and Networks, Manila,Philippines, May, 2002

67)  Wei C. Hsu, Howard Chen, Pen Yew, D-Y. Chen, "On the Predictability of Program Behavior Using Different Input Data Sets" Workshop on interaction between compilers and computer architectures, (INTERACT-6) held with (HPCA-8),Feb.,2002

68)  Bill Blume and Wei Hsu, "FMAC Code Optimization Issues", Workshop on interaction between compilers and computer architectures, International Symposium on High Performance Computer Architecture, (HPCA-3), Feb., 1997, Also published on TCCA Newsletter, June, 1997.

69)  Wei Chung Hsu, "Data Prefetch in PA7200 and PA8000", Workshop on Interaction between Compilers and Computer Architectures, (held with HPCA-2), Feb., 1996.

70)  Wei Chung Hsu, "On Memory Coherency in Parallel Processing", Proceedings of the 14th Modern Engineering and Technology Symposium, 1992.

71)  Wei Chung Hsu, "Aspects of Cache Memories for Cray Computers", Cray Technical Symposium, 1990.

Technical Reports

1) Abhinav Das, Rao Fu, Antonia Zhai, Wei-chung Hsu. "Issues and Support for Dynamic Register Allocation", Technical Report 06-020, Computer Science, University of Minnesota, 2006

2) Sreekumar V. Kodakara, Jinpyo Kim, Wei-chung Hsu, David J. Lilja, Pen-chung Ye. "PASS: Program Structure Aware Stratified Sampling for Statistically Selecting Instruction Traces and Simulation Points", Technical Report 05-044, Computer Science, University of Minnesota, 2005

3) Sourabh Joshi, Wei-Chung Hsu, Pen-Chung Yew, "Implementation of Trace Optimization and Investigation of Advanced Load Optimization in ADORE", Technical Report 05-027, Computer Science, University of Minnesota, 2005

4) Jinpyo Kim, Sreekumar V. Kodakara, Wei-chung Hsu, David J. Lilja, Pen-chung Yew, "Dynamic Code Region-based Program Phase Classification and Transition Prediction", Technical Report 05-021, Computer Science, University of Minnesota, 2005

5) Aditya Saxena, Wei-chung Hsu, "Dynamic Register Allocation for ADORE Runtime Optimization System", Technical Report 04-044, Computer Science, University of Minnesota, 2004

6) Abhinav Das, Jiwei Lu, Howard Chen, Jinpyo Kim, Pen-Chung Yew, Wei-Chung Hsu, Dong-Yuan Chen, "Performance of Runtime Optimization on BLAST", Technical Report 04-038, Computer Science, University of Minnesota, 2004

7) Ananth Lingamneni, Abhinav Das, Wei-chung Hsu. "PerfView: A Performance Monitoring and Visualization Tool for Intel Itanium Architecture", Technical Report 04-030, Computer Science, University of Minnesota, 2004

8) Xiaoru Dai, Wei-Chung Hsu, Pen-Chung Yew, "A General Compiler Framework for Data Speculation Using DSCM", Technical Report 04-012, Computer Science Department, University of Minnesota, 2004.

9) Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Ju, Tin-Fook Ngai, "A Compiler Framework for Recovery Code Generation in General Speculative Optimizations", Technical Report 03-051, Computer Science Department, University of Minnesota, 2003.

10) Wei-Chung Hsu, Howard Chen, Pen Chung Yew, Dong Yuan Chen, "Phase Locality Detection Using a Branch Trace Buffer for Efficient Profiling in Dynamic Optimization", Technical Report TR 02-006, Computer Science Department, University of Minnesota, 2002.

11) Wei-Chung Hsu, "Register Allocation and Code Scheduling for Load/Store Architectures" University of Wisconsin Computer Science Technical Report #722, Oct. 1987.

12) Wei-Chung Hsu, "Register Allocation for VLSI Processors", University of Wisconsin Computer Science Technical Report #619, 1985

 

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