Printable Version
Overview Resources Used
4 | MicroBlaze
1 | Processor Local Bus (PLB) 4.6
8 | Local Memory Bus (LMB) 1.0
16 | Fast Simplex Link (FSL) Bus
5 | Block RAM (BRAM) Block
1 | Multi-Port Memory Controller(DDR/DDR2/SDRAM)
1 | XPS BRAM Controller
4 | LMB BRAM Controller
1 | XPS UART (Lite)
1 | Clock Generator
1 | MicroBlaze Debug Module (MDM)
1 | Processor System Reset Module
1 | XPS System ACE Interface Controller(Compact Flash)
| Specifics
Generated | Tue Jun 24 13:00:24 2014
EDK Version | 13.4
Device Family | virtex5
Device | xc5vlx110tff1136-1
Block Diagram | TOP
External Ports | TOP
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK indicates Clock ports, (SIGIS = CLK) INTR indicates Interrupt ports,(SIGIS = INTR) RESET indicates Reset ports, (SIGIS = RST) BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# | NAME | DIR | [LSB:MSB] | SIG | ATTRIBUTES
SHARED | fpga_0_rst_1_sys_rst_pin | I | 1 | sys_rst_s | RESET
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin | IO | 0:7 | fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_DQS_pin | IO | 0:7 | fpga_0_DDR2_SDRAM_DDR2_DQS_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_DQ_pin | IO | 0:63 | fpga_0_DDR2_SDRAM_DDR2_DQ_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_Addr_pin | O | 0:12 | fpga_0_DDR2_SDRAM_DDR2_Addr_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin | O | 0:1 | fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin | O | 1 | fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_CE_pin | O | 0:1 | fpga_0_DDR2_SDRAM_DDR2_CE_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_CS_n_pin | O | 0:1 | fpga_0_DDR2_SDRAM_DDR2_CS_n_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin | O | 0:1 | fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_Clk_pin | O | 0:1 | fpga_0_DDR2_SDRAM_DDR2_Clk_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_DM_pin | O | 0:7 | fpga_0_DDR2_SDRAM_DDR2_DM_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_ODT_pin | O | 0:1 | fpga_0_DDR2_SDRAM_DDR2_ODT_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin | O | 1 | fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin |
DDR2_SDRAM | fpga_0_DDR2_SDRAM_DDR2_WE_n_pin | O | 1 | fpga_0_DDR2_SDRAM_DDR2_WE_n_pin |
RS232_Uart_1 | fpga_0_RS232_Uart_1_RX_pin | I | 1 | fpga_0_RS232_Uart_1_RX_pin |
RS232_Uart_1 | fpga_0_RS232_Uart_1_TX_pin | O | 1 | fpga_0_RS232_Uart_1_TX_pin |
SysACE_CompactFlash | fpga_0_SysACE_CompactFlash_SysACE_CLK_pin | I | 1 | SysACE_CompactFlash_SysACE_CLK |
SysACE_CompactFlash | fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin | I | 1 | SysACE_CompactFlash_SysACE_MPIRQ |
SysACE_CompactFlash | fpga_0_SysACE_CompactFlash_SysACE_MPD_pin | IO | 0:15 | SysACE_CompactFlash_SysACE_MPD |
SysACE_CompactFlash | fpga_0_SysACE_CompactFlash_SysACE_CEN_pin | O | 1 | SysACE_CompactFlash_SysACE_CEN |
SysACE_CompactFlash | fpga_0_SysACE_CompactFlash_SysACE_MPA_pin | O | 0:6 | SysACE_CompactFlash_SysACE_MPA |
SysACE_CompactFlash | fpga_0_SysACE_CompactFlash_SysACE_OEN_pin | O | 1 | SysACE_CompactFlash_SysACE_OEN |
SysACE_CompactFlash | fpga_0_SysACE_CompactFlash_SysACE_WEN_pin | O | 1 | SysACE_CompactFlash_SysACE_WEN |
clock_generator_0 | fpga_0_clk_1_sys_clk_pin | I | 1 | CLK_S | CLK
Processors | TOP
microblaze_0 MicroBlaze The MicroBlaze 32 bit soft processor
IP Specs
Core | Version | Documentation
microblaze | 8.20.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | MB_RESET | I | 1 | mb_reset
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
IXCL | INITIATOR | XIL_MEMORY_CHANNEL | microblaze_0_IXCL | DDR2_SDRAM
DXCL | INITIATOR | XIL_MEMORY_CHANNEL | microblaze_0_DXCL | DDR2_SDRAM
DPLB | MASTER | PLBV46 | shared_plb | 7 Peripherals.
IPLB | MASTER | PLBV46 | shared_plb | 7 Peripherals.
DLMB | MASTER | LMB | dlmb_0 | bram_cntlr_0
ILMB | MASTER | LMB | ilmb_0 | bram_cntlr_0
MFSL0 | MASTER | FSL | fsl_mb0_to_mutex | shared_mutex
MFSL1 | MASTER | FSL | fsl_mb0_to_tmr | fsl_timer_0
SFSL0 | SLAVE | FSL | fsl_mutex_to_mb0 | shared_mutex
SFSL1 | SLAVE | FSL | fsl_tmr_to_mb0 | fsl_timer_0
DEBUG | TARGET | XIL_MBDEBUG3 | shared_mdm_MBDEBUG_0 | shared_mdm
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_SCO | 0
C_FREQ | 0
C_DATA_SIZE | 32
C_DYNAMIC_BUS_SIZING | 1
C_FAMILY | virtex5
C_INSTANCE | microblaze
C_AVOID_PRIMITIVES | 0
C_FAULT_TOLERANT | 0
C_ECC_USE_CE_EXCEPTION | 0
C_LOCKSTEP_SLAVE | 0
C_ENDIANNESS | 0
C_AREA_OPTIMIZED | 0
C_OPTIMIZATION | 0
C_INTERCONNECT | 1
C_STREAM_INTERCONNECT | 0
C_DPLB_DWIDTH | 32
C_DPLB_NATIVE_DWIDTH | 32
C_DPLB_BURST_EN | 0
C_DPLB_P2P | 0
C_IPLB_DWIDTH | 32
C_IPLB_NATIVE_DWIDTH | 32
C_IPLB_BURST_EN | 0
C_IPLB_P2P | 0
C_M_AXI_DP_SUPPORTS_THREADS | 0
C_M_AXI_DP_THREAD_ID_WIDTH | 1
C_M_AXI_DP_SUPPORTS_READ | 1
C_M_AXI_DP_SUPPORTS_WRITE | 1
C_M_AXI_DP_SUPPORTS_NARROW_BURST | 0
C_M_AXI_DP_DATA_WIDTH | 32
C_M_AXI_DP_ADDR_WIDTH | 32
C_M_AXI_DP_PROTOCOL | AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS | 0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING | 1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING | 1
C_M_AXI_IP_SUPPORTS_THREADS | 0
C_M_AXI_IP_THREAD_ID_WIDTH | 1
C_M_AXI_IP_SUPPORTS_READ | 1
C_M_AXI_IP_SUPPORTS_WRITE | 0
C_M_AXI_IP_SUPPORTS_NARROW_BURST | 0
C_M_AXI_IP_DATA_WIDTH | 32
C_M_AXI_IP_ADDR_WIDTH | 32
C_M_AXI_IP_PROTOCOL | AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING | 1
C_D_AXI | 0
C_D_PLB | 0
C_D_LMB | 1
C_I_AXI | 0
C_I_PLB | 0
C_I_LMB | 1
C_USE_MSR_INSTR | 1
C_USE_PCMP_INSTR | 1
C_USE_BARREL | 1
C_USE_DIV | 1
C_USE_HW_MUL | 1
C_USE_FPU | 0
C_UNALIGNED_EXCEPTIONS | 0
C_ILL_OPCODE_EXCEPTION | 0
C_M_AXI_I_BUS_EXCEPTION | 0
C_M_AXI_D_BUS_EXCEPTION | 0
C_IPLB_BUS_EXCEPTION | 0
C_DPLB_BUS_EXCEPTION | 0
C_DIV_ZERO_EXCEPTION | 0
C_FPU_EXCEPTION | 0
C_FSL_EXCEPTION | 0
C_USE_STACK_PROTECTION | 0
C_PVR | 1
C_PVR_USER1 | 0x00
C_PVR_USER2 | 0x00000000
C_DEBUG_ENABLED | 1
C_NUMBER_OF_PC_BRK | 1
C_NUMBER_OF_RD_ADDR_BRK | 0
C_NUMBER_OF_WR_ADDR_BRK | 0
C_INTERRUPT_IS_EDGE | 0
C_EDGE_IS_POSITIVE | 1
C_RESET_MSR | 0x00000000
C_OPCODE_0x0_ILLEGAL | 0
C_FSL_LINKS | 2
C_FSL_DATA_SIZE | 32
C_USE_EXTENDED_FSL_INSTR | 1
C_M0_AXIS_PROTOCOL | GENERIC
C_S0_AXIS_PROTOCOL | GENERIC
C_M1_AXIS_PROTOCOL | GENERIC
C_S1_AXIS_PROTOCOL | GENERIC
C_M2_AXIS_PROTOCOL | GENERIC
C_S2_AXIS_PROTOCOL | GENERIC
C_M3_AXIS_PROTOCOL | GENERIC
C_S3_AXIS_PROTOCOL | GENERIC
C_M4_AXIS_PROTOCOL | GENERIC
C_S4_AXIS_PROTOCOL | GENERIC
C_M5_AXIS_PROTOCOL | GENERIC
C_S5_AXIS_PROTOCOL | GENERIC
C_M6_AXIS_PROTOCOL | GENERIC
C_S6_AXIS_PROTOCOL | GENERIC
C_M7_AXIS_PROTOCOL | GENERIC
C_S7_AXIS_PROTOCOL | GENERIC
C_M8_AXIS_PROTOCOL | GENERIC
C_S8_AXIS_PROTOCOL | GENERIC
C_M9_AXIS_PROTOCOL | GENERIC
C_S9_AXIS_PROTOCOL | GENERIC
C_M10_AXIS_PROTOCOL | GENERIC
C_S10_AXIS_PROTOCOL | GENERIC
C_M11_AXIS_PROTOCOL | GENERIC
C_S11_AXIS_PROTOCOL | GENERIC
C_M12_AXIS_PROTOCOL | GENERIC
C_S12_AXIS_PROTOCOL | GENERIC
C_M13_AXIS_PROTOCOL | GENERIC
C_S13_AXIS_PROTOCOL | GENERIC
C_M14_AXIS_PROTOCOL | GENERIC |  | Name | Value
C_S14_AXIS_PROTOCOL | GENERIC
C_M15_AXIS_PROTOCOL | GENERIC
C_S15_AXIS_PROTOCOL | GENERIC
C_M0_AXIS_DATA_WIDTH | 32
C_S0_AXIS_DATA_WIDTH | 32
C_M1_AXIS_DATA_WIDTH | 32
C_S1_AXIS_DATA_WIDTH | 32
C_M2_AXIS_DATA_WIDTH | 32
C_S2_AXIS_DATA_WIDTH | 32
C_M3_AXIS_DATA_WIDTH | 32
C_S3_AXIS_DATA_WIDTH | 32
C_M4_AXIS_DATA_WIDTH | 32
C_S4_AXIS_DATA_WIDTH | 32
C_M5_AXIS_DATA_WIDTH | 32
C_S5_AXIS_DATA_WIDTH | 32
C_M6_AXIS_DATA_WIDTH | 32
C_S6_AXIS_DATA_WIDTH | 32
C_M7_AXIS_DATA_WIDTH | 32
C_S7_AXIS_DATA_WIDTH | 32
C_M8_AXIS_DATA_WIDTH | 32
C_S8_AXIS_DATA_WIDTH | 32
C_M9_AXIS_DATA_WIDTH | 32
C_S9_AXIS_DATA_WIDTH | 32
C_M10_AXIS_DATA_WIDTH | 32
C_S10_AXIS_DATA_WIDTH | 32
C_M11_AXIS_DATA_WIDTH | 32
C_S11_AXIS_DATA_WIDTH | 32
C_M12_AXIS_DATA_WIDTH | 32
C_S12_AXIS_DATA_WIDTH | 32
C_M13_AXIS_DATA_WIDTH | 32
C_S13_AXIS_DATA_WIDTH | 32
C_M14_AXIS_DATA_WIDTH | 32
C_S14_AXIS_DATA_WIDTH | 32
C_M15_AXIS_DATA_WIDTH | 32
C_S15_AXIS_DATA_WIDTH | 32
C_ICACHE_BASEADDR | 0x90000000
C_ICACHE_HIGHADDR | 0x9FFFFFFF
C_USE_ICACHE | 1
C_ALLOW_ICACHE_WR | 1
C_ADDR_TAG_BITS | 17
C_CACHE_BYTE_SIZE | 8192
C_ICACHE_USE_FSL | 1
C_ICACHE_LINE_LEN | 4
C_ICACHE_ALWAYS_USED | 1
C_ICACHE_INTERFACE | 0
C_ICACHE_VICTIMS | 0
C_ICACHE_STREAMS | 0
C_ICACHE_FORCE_TAG_LUTRAM | 0
C_ICACHE_DATA_WIDTH | 0
C_M_AXI_IC_SUPPORTS_THREADS | 0
C_M_AXI_IC_THREAD_ID_WIDTH | 1
C_M_AXI_IC_SUPPORTS_READ | 1
C_M_AXI_IC_SUPPORTS_WRITE | 0
C_M_AXI_IC_SUPPORTS_NARROW_BURST | 0
C_M_AXI_IC_DATA_WIDTH | 32
C_M_AXI_IC_ADDR_WIDTH | 32
C_M_AXI_IC_PROTOCOL | AXI4
C_M_AXI_IC_USER_VALUE | 0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS | 1
C_M_AXI_IC_AWUSER_WIDTH | 5
C_M_AXI_IC_ARUSER_WIDTH | 5
C_M_AXI_IC_WUSER_WIDTH | 1
C_M_AXI_IC_RUSER_WIDTH | 1
C_M_AXI_IC_BUSER_WIDTH | 1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING | 2
C_DCACHE_BASEADDR | 0x90000000
C_DCACHE_HIGHADDR | 0x9FFFFFFF
C_USE_DCACHE | 1
C_ALLOW_DCACHE_WR | 1
C_DCACHE_ADDR_TAG | 17
C_DCACHE_BYTE_SIZE | 16384
C_DCACHE_USE_FSL | 1
C_DCACHE_LINE_LEN | 4
C_DCACHE_ALWAYS_USED | 1
C_DCACHE_INTERFACE | 0
C_DCACHE_USE_WRITEBACK | 0
C_DCACHE_VICTIMS | 0
C_DCACHE_FORCE_TAG_LUTRAM | 0
C_DCACHE_DATA_WIDTH | 0
C_M_AXI_DC_SUPPORTS_THREADS | 0
C_M_AXI_DC_THREAD_ID_WIDTH | 1
C_M_AXI_DC_SUPPORTS_READ | 1
C_M_AXI_DC_SUPPORTS_WRITE | 1
C_M_AXI_DC_SUPPORTS_NARROW_BURST | 0
C_M_AXI_DC_DATA_WIDTH | 32
C_M_AXI_DC_ADDR_WIDTH | 32
C_M_AXI_DC_PROTOCOL | AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS | 0
C_M_AXI_DC_USER_VALUE | 0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS | 1
C_M_AXI_DC_AWUSER_WIDTH | 5
C_M_AXI_DC_ARUSER_WIDTH | 5
C_M_AXI_DC_WUSER_WIDTH | 1
C_M_AXI_DC_RUSER_WIDTH | 1
C_M_AXI_DC_BUSER_WIDTH | 1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING | 2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING | 32
C_USE_MMU | 0
C_MMU_DTLB_SIZE | 4
C_MMU_ITLB_SIZE | 2
C_MMU_TLB_ACCESS | 3
C_MMU_ZONES | 16
C_MMU_PRIVILEGED_INSTR | 0
C_USE_INTERRUPT | 0
C_USE_EXT_BRK | 0
C_USE_EXT_NM_BRK | 0
C_USE_BRANCH_TARGET_CACHE | 0
C_BRANCH_TARGET_CACHE_SIZE | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
microblaze_1 MicroBlaze The MicroBlaze 32 bit soft processor
IP Specs
Core | Version | Documentation
microblaze | 8.20.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | MB_RESET | I | 1 | mb_reset
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
IXCL | INITIATOR | XIL_MEMORY_CHANNEL | microblaze_1_IXCL | DDR2_SDRAM
DXCL | INITIATOR | XIL_MEMORY_CHANNEL | microblaze_1_DXCL | DDR2_SDRAM
DPLB | MASTER | PLBV46 | shared_plb | 7 Peripherals.
IPLB | MASTER | PLBV46 | shared_plb | 7 Peripherals.
DLMB | MASTER | LMB | dlmb_1 | bram_cntlr_1
ILMB | MASTER | LMB | ilmb_1 | bram_cntlr_1
MFSL0 | MASTER | FSL | fsl_mb1_to_mutex | shared_mutex
MFSL1 | MASTER | FSL | fsl_mb1_to_tmr | fsl_timer_0
SFSL0 | SLAVE | FSL | fsl_mutex_to_mb1 | shared_mutex
SFSL1 | SLAVE | FSL | fsl_tmr_to_mb1 | fsl_timer_0
DEBUG | TARGET | XIL_MBDEBUG3 | shared_mdm_MBDEBUG_1 | shared_mdm
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_SCO | 0
C_FREQ | 0
C_DATA_SIZE | 32
C_DYNAMIC_BUS_SIZING | 1
C_FAMILY | virtex5
C_INSTANCE | microblaze
C_AVOID_PRIMITIVES | 0
C_FAULT_TOLERANT | 0
C_ECC_USE_CE_EXCEPTION | 0
C_LOCKSTEP_SLAVE | 0
C_ENDIANNESS | 0
C_AREA_OPTIMIZED | 0
C_OPTIMIZATION | 0
C_INTERCONNECT | 1
C_STREAM_INTERCONNECT | 0
C_DPLB_DWIDTH | 32
C_DPLB_NATIVE_DWIDTH | 32
C_DPLB_BURST_EN | 0
C_DPLB_P2P | 0
C_IPLB_DWIDTH | 32
C_IPLB_NATIVE_DWIDTH | 32
C_IPLB_BURST_EN | 0
C_IPLB_P2P | 0
C_M_AXI_DP_SUPPORTS_THREADS | 0
C_M_AXI_DP_THREAD_ID_WIDTH | 1
C_M_AXI_DP_SUPPORTS_READ | 1
C_M_AXI_DP_SUPPORTS_WRITE | 1
C_M_AXI_DP_SUPPORTS_NARROW_BURST | 0
C_M_AXI_DP_DATA_WIDTH | 32
C_M_AXI_DP_ADDR_WIDTH | 32
C_M_AXI_DP_PROTOCOL | AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS | 0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING | 1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING | 1
C_M_AXI_IP_SUPPORTS_THREADS | 0
C_M_AXI_IP_THREAD_ID_WIDTH | 1
C_M_AXI_IP_SUPPORTS_READ | 1
C_M_AXI_IP_SUPPORTS_WRITE | 0
C_M_AXI_IP_SUPPORTS_NARROW_BURST | 0
C_M_AXI_IP_DATA_WIDTH | 32
C_M_AXI_IP_ADDR_WIDTH | 32
C_M_AXI_IP_PROTOCOL | AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING | 1
C_D_AXI | 0
C_D_PLB | 0
C_D_LMB | 1
C_I_AXI | 0
C_I_PLB | 0
C_I_LMB | 1
C_USE_MSR_INSTR | 1
C_USE_PCMP_INSTR | 1
C_USE_BARREL | 1
C_USE_DIV | 1
C_USE_HW_MUL | 1
C_USE_FPU | 0
C_UNALIGNED_EXCEPTIONS | 0
C_ILL_OPCODE_EXCEPTION | 0
C_M_AXI_I_BUS_EXCEPTION | 0
C_M_AXI_D_BUS_EXCEPTION | 0
C_IPLB_BUS_EXCEPTION | 0
C_DPLB_BUS_EXCEPTION | 0
C_DIV_ZERO_EXCEPTION | 0
C_FPU_EXCEPTION | 0
C_FSL_EXCEPTION | 0
C_USE_STACK_PROTECTION | 0
C_PVR | 1
C_PVR_USER1 | 0x01
C_PVR_USER2 | 0x00000000
C_DEBUG_ENABLED | 1
C_NUMBER_OF_PC_BRK | 1
C_NUMBER_OF_RD_ADDR_BRK | 0
C_NUMBER_OF_WR_ADDR_BRK | 0
C_INTERRUPT_IS_EDGE | 0
C_EDGE_IS_POSITIVE | 1
C_RESET_MSR | 0x00000000
C_OPCODE_0x0_ILLEGAL | 0
C_FSL_LINKS | 2
C_FSL_DATA_SIZE | 32
C_USE_EXTENDED_FSL_INSTR | 1
C_M0_AXIS_PROTOCOL | GENERIC
C_S0_AXIS_PROTOCOL | GENERIC
C_M1_AXIS_PROTOCOL | GENERIC
C_S1_AXIS_PROTOCOL | GENERIC
C_M2_AXIS_PROTOCOL | GENERIC
C_S2_AXIS_PROTOCOL | GENERIC
C_M3_AXIS_PROTOCOL | GENERIC
C_S3_AXIS_PROTOCOL | GENERIC
C_M4_AXIS_PROTOCOL | GENERIC
C_S4_AXIS_PROTOCOL | GENERIC
C_M5_AXIS_PROTOCOL | GENERIC
C_S5_AXIS_PROTOCOL | GENERIC
C_M6_AXIS_PROTOCOL | GENERIC
C_S6_AXIS_PROTOCOL | GENERIC
C_M7_AXIS_PROTOCOL | GENERIC
C_S7_AXIS_PROTOCOL | GENERIC
C_M8_AXIS_PROTOCOL | GENERIC
C_S8_AXIS_PROTOCOL | GENERIC
C_M9_AXIS_PROTOCOL | GENERIC
C_S9_AXIS_PROTOCOL | GENERIC
C_M10_AXIS_PROTOCOL | GENERIC
C_S10_AXIS_PROTOCOL | GENERIC
C_M11_AXIS_PROTOCOL | GENERIC
C_S11_AXIS_PROTOCOL | GENERIC
C_M12_AXIS_PROTOCOL | GENERIC
C_S12_AXIS_PROTOCOL | GENERIC
C_M13_AXIS_PROTOCOL | GENERIC
C_S13_AXIS_PROTOCOL | GENERIC
C_M14_AXIS_PROTOCOL | GENERIC |  | Name | Value
C_S14_AXIS_PROTOCOL | GENERIC
C_M15_AXIS_PROTOCOL | GENERIC
C_S15_AXIS_PROTOCOL | GENERIC
C_M0_AXIS_DATA_WIDTH | 32
C_S0_AXIS_DATA_WIDTH | 32
C_M1_AXIS_DATA_WIDTH | 32
C_S1_AXIS_DATA_WIDTH | 32
C_M2_AXIS_DATA_WIDTH | 32
C_S2_AXIS_DATA_WIDTH | 32
C_M3_AXIS_DATA_WIDTH | 32
C_S3_AXIS_DATA_WIDTH | 32
C_M4_AXIS_DATA_WIDTH | 32
C_S4_AXIS_DATA_WIDTH | 32
C_M5_AXIS_DATA_WIDTH | 32
C_S5_AXIS_DATA_WIDTH | 32
C_M6_AXIS_DATA_WIDTH | 32
C_S6_AXIS_DATA_WIDTH | 32
C_M7_AXIS_DATA_WIDTH | 32
C_S7_AXIS_DATA_WIDTH | 32
C_M8_AXIS_DATA_WIDTH | 32
C_S8_AXIS_DATA_WIDTH | 32
C_M9_AXIS_DATA_WIDTH | 32
C_S9_AXIS_DATA_WIDTH | 32
C_M10_AXIS_DATA_WIDTH | 32
C_S10_AXIS_DATA_WIDTH | 32
C_M11_AXIS_DATA_WIDTH | 32
C_S11_AXIS_DATA_WIDTH | 32
C_M12_AXIS_DATA_WIDTH | 32
C_S12_AXIS_DATA_WIDTH | 32
C_M13_AXIS_DATA_WIDTH | 32
C_S13_AXIS_DATA_WIDTH | 32
C_M14_AXIS_DATA_WIDTH | 32
C_S14_AXIS_DATA_WIDTH | 32
C_M15_AXIS_DATA_WIDTH | 32
C_S15_AXIS_DATA_WIDTH | 32
C_ICACHE_BASEADDR | 0x90000000
C_ICACHE_HIGHADDR | 0x9FFFFFFF
C_USE_ICACHE | 1
C_ALLOW_ICACHE_WR | 1
C_ADDR_TAG_BITS | 17
C_CACHE_BYTE_SIZE | 8192
C_ICACHE_USE_FSL | 1
C_ICACHE_LINE_LEN | 4
C_ICACHE_ALWAYS_USED | 1
C_ICACHE_INTERFACE | 0
C_ICACHE_VICTIMS | 0
C_ICACHE_STREAMS | 0
C_ICACHE_FORCE_TAG_LUTRAM | 0
C_ICACHE_DATA_WIDTH | 0
C_M_AXI_IC_SUPPORTS_THREADS | 0
C_M_AXI_IC_THREAD_ID_WIDTH | 1
C_M_AXI_IC_SUPPORTS_READ | 1
C_M_AXI_IC_SUPPORTS_WRITE | 0
C_M_AXI_IC_SUPPORTS_NARROW_BURST | 0
C_M_AXI_IC_DATA_WIDTH | 32
C_M_AXI_IC_ADDR_WIDTH | 32
C_M_AXI_IC_PROTOCOL | AXI4
C_M_AXI_IC_USER_VALUE | 0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS | 1
C_M_AXI_IC_AWUSER_WIDTH | 5
C_M_AXI_IC_ARUSER_WIDTH | 5
C_M_AXI_IC_WUSER_WIDTH | 1
C_M_AXI_IC_RUSER_WIDTH | 1
C_M_AXI_IC_BUSER_WIDTH | 1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING | 2
C_DCACHE_BASEADDR | 0x90000000
C_DCACHE_HIGHADDR | 0x9FFFFFFF
C_USE_DCACHE | 1
C_ALLOW_DCACHE_WR | 1
C_DCACHE_ADDR_TAG | 17
C_DCACHE_BYTE_SIZE | 16384
C_DCACHE_USE_FSL | 1
C_DCACHE_LINE_LEN | 4
C_DCACHE_ALWAYS_USED | 1
C_DCACHE_INTERFACE | 0
C_DCACHE_USE_WRITEBACK | 0
C_DCACHE_VICTIMS | 0
C_DCACHE_FORCE_TAG_LUTRAM | 0
C_DCACHE_DATA_WIDTH | 0
C_M_AXI_DC_SUPPORTS_THREADS | 0
C_M_AXI_DC_THREAD_ID_WIDTH | 1
C_M_AXI_DC_SUPPORTS_READ | 1
C_M_AXI_DC_SUPPORTS_WRITE | 1
C_M_AXI_DC_SUPPORTS_NARROW_BURST | 0
C_M_AXI_DC_DATA_WIDTH | 32
C_M_AXI_DC_ADDR_WIDTH | 32
C_M_AXI_DC_PROTOCOL | AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS | 0
C_M_AXI_DC_USER_VALUE | 0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS | 1
C_M_AXI_DC_AWUSER_WIDTH | 5
C_M_AXI_DC_ARUSER_WIDTH | 5
C_M_AXI_DC_WUSER_WIDTH | 1
C_M_AXI_DC_RUSER_WIDTH | 1
C_M_AXI_DC_BUSER_WIDTH | 1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING | 2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING | 32
C_USE_MMU | 0
C_MMU_DTLB_SIZE | 4
C_MMU_ITLB_SIZE | 2
C_MMU_TLB_ACCESS | 3
C_MMU_ZONES | 16
C_MMU_PRIVILEGED_INSTR | 0
C_USE_INTERRUPT | 0
C_USE_EXT_BRK | 0
C_USE_EXT_NM_BRK | 0
C_USE_BRANCH_TARGET_CACHE | 0
C_BRANCH_TARGET_CACHE_SIZE | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
microblaze_2 MicroBlaze The MicroBlaze 32 bit soft processor
IP Specs
Core | Version | Documentation
microblaze | 8.20.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | MB_RESET | I | 1 | mb_reset
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
IXCL | INITIATOR | XIL_MEMORY_CHANNEL | microblaze_2_IXCL | DDR2_SDRAM
DXCL | INITIATOR | XIL_MEMORY_CHANNEL | microblaze_2_DXCL | DDR2_SDRAM
DPLB | MASTER | PLBV46 | shared_plb | 7 Peripherals.
IPLB | MASTER | PLBV46 | shared_plb | 7 Peripherals.
DLMB | MASTER | LMB | dlmb_2 | bram_cntlr_2
ILMB | MASTER | LMB | ilmb_2 | bram_cntlr_2
MFSL0 | MASTER | FSL | fsl_mb2_to_mutex | shared_mutex
MFSL1 | MASTER | FSL | fsl_mb2_to_tmr | fsl_timer_0
SFSL0 | SLAVE | FSL | fsl_mutex_to_mb2 | shared_mutex
SFSL1 | SLAVE | FSL | fsl_tmr_to_mb2 | fsl_timer_0
DEBUG | TARGET | XIL_MBDEBUG3 | shared_mdm_MBDEBUG_2 | shared_mdm
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_SCO | 0
C_FREQ | 0
C_DATA_SIZE | 32
C_DYNAMIC_BUS_SIZING | 1
C_FAMILY | virtex5
C_INSTANCE | microblaze
C_AVOID_PRIMITIVES | 0
C_FAULT_TOLERANT | 0
C_ECC_USE_CE_EXCEPTION | 0
C_LOCKSTEP_SLAVE | 0
C_ENDIANNESS | 0
C_AREA_OPTIMIZED | 0
C_OPTIMIZATION | 0
C_INTERCONNECT | 1
C_STREAM_INTERCONNECT | 0
C_DPLB_DWIDTH | 32
C_DPLB_NATIVE_DWIDTH | 32
C_DPLB_BURST_EN | 0
C_DPLB_P2P | 0
C_IPLB_DWIDTH | 32
C_IPLB_NATIVE_DWIDTH | 32
C_IPLB_BURST_EN | 0
C_IPLB_P2P | 0
C_M_AXI_DP_SUPPORTS_THREADS | 0
C_M_AXI_DP_THREAD_ID_WIDTH | 1
C_M_AXI_DP_SUPPORTS_READ | 1
C_M_AXI_DP_SUPPORTS_WRITE | 1
C_M_AXI_DP_SUPPORTS_NARROW_BURST | 0
C_M_AXI_DP_DATA_WIDTH | 32
C_M_AXI_DP_ADDR_WIDTH | 32
C_M_AXI_DP_PROTOCOL | AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS | 0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING | 1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING | 1
C_M_AXI_IP_SUPPORTS_THREADS | 0
C_M_AXI_IP_THREAD_ID_WIDTH | 1
C_M_AXI_IP_SUPPORTS_READ | 1
C_M_AXI_IP_SUPPORTS_WRITE | 0
C_M_AXI_IP_SUPPORTS_NARROW_BURST | 0
C_M_AXI_IP_DATA_WIDTH | 32
C_M_AXI_IP_ADDR_WIDTH | 32
C_M_AXI_IP_PROTOCOL | AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING | 1
C_D_AXI | 0
C_D_PLB | 0
C_D_LMB | 1
C_I_AXI | 0
C_I_PLB | 0
C_I_LMB | 1
C_USE_MSR_INSTR | 1
C_USE_PCMP_INSTR | 1
C_USE_BARREL | 1
C_USE_DIV | 1
C_USE_HW_MUL | 1
C_USE_FPU | 0
C_UNALIGNED_EXCEPTIONS | 0
C_ILL_OPCODE_EXCEPTION | 0
C_M_AXI_I_BUS_EXCEPTION | 0
C_M_AXI_D_BUS_EXCEPTION | 0
C_IPLB_BUS_EXCEPTION | 0
C_DPLB_BUS_EXCEPTION | 0
C_DIV_ZERO_EXCEPTION | 0
C_FPU_EXCEPTION | 0
C_FSL_EXCEPTION | 0
C_USE_STACK_PROTECTION | 0
C_PVR | 1
C_PVR_USER1 | 0x02
C_PVR_USER2 | 0x00000000
C_DEBUG_ENABLED | 1
C_NUMBER_OF_PC_BRK | 1
C_NUMBER_OF_RD_ADDR_BRK | 0
C_NUMBER_OF_WR_ADDR_BRK | 0
C_INTERRUPT_IS_EDGE | 0
C_EDGE_IS_POSITIVE | 1
C_RESET_MSR | 0x00000000
C_OPCODE_0x0_ILLEGAL | 0
C_FSL_LINKS | 2
C_FSL_DATA_SIZE | 32
C_USE_EXTENDED_FSL_INSTR | 1
C_M0_AXIS_PROTOCOL | GENERIC
C_S0_AXIS_PROTOCOL | GENERIC
C_M1_AXIS_PROTOCOL | GENERIC
C_S1_AXIS_PROTOCOL | GENERIC
C_M2_AXIS_PROTOCOL | GENERIC
C_S2_AXIS_PROTOCOL | GENERIC
C_M3_AXIS_PROTOCOL | GENERIC
C_S3_AXIS_PROTOCOL | GENERIC
C_M4_AXIS_PROTOCOL | GENERIC
C_S4_AXIS_PROTOCOL | GENERIC
C_M5_AXIS_PROTOCOL | GENERIC
C_S5_AXIS_PROTOCOL | GENERIC
C_M6_AXIS_PROTOCOL | GENERIC
C_S6_AXIS_PROTOCOL | GENERIC
C_M7_AXIS_PROTOCOL | GENERIC
C_S7_AXIS_PROTOCOL | GENERIC
C_M8_AXIS_PROTOCOL | GENERIC
C_S8_AXIS_PROTOCOL | GENERIC
C_M9_AXIS_PROTOCOL | GENERIC
C_S9_AXIS_PROTOCOL | GENERIC
C_M10_AXIS_PROTOCOL | GENERIC
C_S10_AXIS_PROTOCOL | GENERIC
C_M11_AXIS_PROTOCOL | GENERIC
C_S11_AXIS_PROTOCOL | GENERIC
C_M12_AXIS_PROTOCOL | GENERIC
C_S12_AXIS_PROTOCOL | GENERIC
C_M13_AXIS_PROTOCOL | GENERIC
C_S13_AXIS_PROTOCOL | GENERIC
C_M14_AXIS_PROTOCOL | GENERIC |  | Name | Value
C_S14_AXIS_PROTOCOL | GENERIC
C_M15_AXIS_PROTOCOL | GENERIC
C_S15_AXIS_PROTOCOL | GENERIC
C_M0_AXIS_DATA_WIDTH | 32
C_S0_AXIS_DATA_WIDTH | 32
C_M1_AXIS_DATA_WIDTH | 32
C_S1_AXIS_DATA_WIDTH | 32
C_M2_AXIS_DATA_WIDTH | 32
C_S2_AXIS_DATA_WIDTH | 32
C_M3_AXIS_DATA_WIDTH | 32
C_S3_AXIS_DATA_WIDTH | 32
C_M4_AXIS_DATA_WIDTH | 32
C_S4_AXIS_DATA_WIDTH | 32
C_M5_AXIS_DATA_WIDTH | 32
C_S5_AXIS_DATA_WIDTH | 32
C_M6_AXIS_DATA_WIDTH | 32
C_S6_AXIS_DATA_WIDTH | 32
C_M7_AXIS_DATA_WIDTH | 32
C_S7_AXIS_DATA_WIDTH | 32
C_M8_AXIS_DATA_WIDTH | 32
C_S8_AXIS_DATA_WIDTH | 32
C_M9_AXIS_DATA_WIDTH | 32
C_S9_AXIS_DATA_WIDTH | 32
C_M10_AXIS_DATA_WIDTH | 32
C_S10_AXIS_DATA_WIDTH | 32
C_M11_AXIS_DATA_WIDTH | 32
C_S11_AXIS_DATA_WIDTH | 32
C_M12_AXIS_DATA_WIDTH | 32
C_S12_AXIS_DATA_WIDTH | 32
C_M13_AXIS_DATA_WIDTH | 32
C_S13_AXIS_DATA_WIDTH | 32
C_M14_AXIS_DATA_WIDTH | 32
C_S14_AXIS_DATA_WIDTH | 32
C_M15_AXIS_DATA_WIDTH | 32
C_S15_AXIS_DATA_WIDTH | 32
C_ICACHE_BASEADDR | 0x90000000
C_ICACHE_HIGHADDR | 0x9FFFFFFF
C_USE_ICACHE | 1
C_ALLOW_ICACHE_WR | 1
C_ADDR_TAG_BITS | 17
C_CACHE_BYTE_SIZE | 8192
C_ICACHE_USE_FSL | 1
C_ICACHE_LINE_LEN | 4
C_ICACHE_ALWAYS_USED | 1
C_ICACHE_INTERFACE | 0
C_ICACHE_VICTIMS | 0
C_ICACHE_STREAMS | 0
C_ICACHE_FORCE_TAG_LUTRAM | 0
C_ICACHE_DATA_WIDTH | 0
C_M_AXI_IC_SUPPORTS_THREADS | 0
C_M_AXI_IC_THREAD_ID_WIDTH | 1
C_M_AXI_IC_SUPPORTS_READ | 1
C_M_AXI_IC_SUPPORTS_WRITE | 0
C_M_AXI_IC_SUPPORTS_NARROW_BURST | 0
C_M_AXI_IC_DATA_WIDTH | 32
C_M_AXI_IC_ADDR_WIDTH | 32
C_M_AXI_IC_PROTOCOL | AXI4
C_M_AXI_IC_USER_VALUE | 0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS | 1
C_M_AXI_IC_AWUSER_WIDTH | 5
C_M_AXI_IC_ARUSER_WIDTH | 5
C_M_AXI_IC_WUSER_WIDTH | 1
C_M_AXI_IC_RUSER_WIDTH | 1
C_M_AXI_IC_BUSER_WIDTH | 1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING | 2
C_DCACHE_BASEADDR | 0x90000000
C_DCACHE_HIGHADDR | 0x9FFFFFFF
C_USE_DCACHE | 1
C_ALLOW_DCACHE_WR | 1
C_DCACHE_ADDR_TAG | 17
C_DCACHE_BYTE_SIZE | 16384
C_DCACHE_USE_FSL | 1
C_DCACHE_LINE_LEN | 4
C_DCACHE_ALWAYS_USED | 1
C_DCACHE_INTERFACE | 0
C_DCACHE_USE_WRITEBACK | 0
C_DCACHE_VICTIMS | 0
C_DCACHE_FORCE_TAG_LUTRAM | 0
C_DCACHE_DATA_WIDTH | 0
C_M_AXI_DC_SUPPORTS_THREADS | 0
C_M_AXI_DC_THREAD_ID_WIDTH | 1
C_M_AXI_DC_SUPPORTS_READ | 1
C_M_AXI_DC_SUPPORTS_WRITE | 1
C_M_AXI_DC_SUPPORTS_NARROW_BURST | 0
C_M_AXI_DC_DATA_WIDTH | 32
C_M_AXI_DC_ADDR_WIDTH | 32
C_M_AXI_DC_PROTOCOL | AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS | 0
C_M_AXI_DC_USER_VALUE | 0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS | 1
C_M_AXI_DC_AWUSER_WIDTH | 5
C_M_AXI_DC_ARUSER_WIDTH | 5
C_M_AXI_DC_WUSER_WIDTH | 1
C_M_AXI_DC_RUSER_WIDTH | 1
C_M_AXI_DC_BUSER_WIDTH | 1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING | 2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING | 32
C_USE_MMU | 0
C_MMU_DTLB_SIZE | 4
C_MMU_ITLB_SIZE | 2
C_MMU_TLB_ACCESS | 3
C_MMU_ZONES | 16
C_MMU_PRIVILEGED_INSTR | 0
C_USE_INTERRUPT | 0
C_USE_EXT_BRK | 0
C_USE_EXT_NM_BRK | 0
C_USE_BRANCH_TARGET_CACHE | 0
C_BRANCH_TARGET_CACHE_SIZE | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
microblaze_3 MicroBlaze The MicroBlaze 32 bit soft processor
IP Specs
Core | Version | Documentation
microblaze | 8.20.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | MB_RESET | I | 1 | mb_reset
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
IXCL | INITIATOR | XIL_MEMORY_CHANNEL | microblaze_3_IXCL | DDR2_SDRAM
DXCL | INITIATOR | XIL_MEMORY_CHANNEL | microblaze_3_DXCL | DDR2_SDRAM
DPLB | MASTER | PLBV46 | shared_plb | 7 Peripherals.
IPLB | MASTER | PLBV46 | shared_plb | 7 Peripherals.
DLMB | MASTER | LMB | dlmb_3 | bram_cntlr_3
ILMB | MASTER | LMB | ilmb_3 | bram_cntlr_3
MFSL0 | MASTER | FSL | fsl_mb3_to_mutex | shared_mutex
MFSL1 | MASTER | FSL | fsl_mb3_to_tmr | fsl_timer_0
SFSL0 | SLAVE | FSL | fsl_mutex_to_mb3 | shared_mutex
SFSL1 | SLAVE | FSL | fsl_tmr_to_mb3 | fsl_timer_0
DEBUG | TARGET | XIL_MBDEBUG3 | shared_mdm_MBDEBUG_3 | shared_mdm
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_SCO | 0
C_FREQ | 0
C_DATA_SIZE | 32
C_DYNAMIC_BUS_SIZING | 1
C_FAMILY | virtex5
C_INSTANCE | microblaze
C_AVOID_PRIMITIVES | 0
C_FAULT_TOLERANT | 0
C_ECC_USE_CE_EXCEPTION | 0
C_LOCKSTEP_SLAVE | 0
C_ENDIANNESS | 0
C_AREA_OPTIMIZED | 0
C_OPTIMIZATION | 0
C_INTERCONNECT | 1
C_STREAM_INTERCONNECT | 0
C_DPLB_DWIDTH | 32
C_DPLB_NATIVE_DWIDTH | 32
C_DPLB_BURST_EN | 0
C_DPLB_P2P | 0
C_IPLB_DWIDTH | 32
C_IPLB_NATIVE_DWIDTH | 32
C_IPLB_BURST_EN | 0
C_IPLB_P2P | 0
C_M_AXI_DP_SUPPORTS_THREADS | 0
C_M_AXI_DP_THREAD_ID_WIDTH | 1
C_M_AXI_DP_SUPPORTS_READ | 1
C_M_AXI_DP_SUPPORTS_WRITE | 1
C_M_AXI_DP_SUPPORTS_NARROW_BURST | 0
C_M_AXI_DP_DATA_WIDTH | 32
C_M_AXI_DP_ADDR_WIDTH | 32
C_M_AXI_DP_PROTOCOL | AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS | 0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING | 1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING | 1
C_M_AXI_IP_SUPPORTS_THREADS | 0
C_M_AXI_IP_THREAD_ID_WIDTH | 1
C_M_AXI_IP_SUPPORTS_READ | 1
C_M_AXI_IP_SUPPORTS_WRITE | 0
C_M_AXI_IP_SUPPORTS_NARROW_BURST | 0
C_M_AXI_IP_DATA_WIDTH | 32
C_M_AXI_IP_ADDR_WIDTH | 32
C_M_AXI_IP_PROTOCOL | AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING | 1
C_D_AXI | 0
C_D_PLB | 0
C_D_LMB | 1
C_I_AXI | 0
C_I_PLB | 0
C_I_LMB | 1
C_USE_MSR_INSTR | 1
C_USE_PCMP_INSTR | 1
C_USE_BARREL | 1
C_USE_DIV | 1
C_USE_HW_MUL | 1
C_USE_FPU | 0
C_UNALIGNED_EXCEPTIONS | 0
C_ILL_OPCODE_EXCEPTION | 0
C_M_AXI_I_BUS_EXCEPTION | 0
C_M_AXI_D_BUS_EXCEPTION | 0
C_IPLB_BUS_EXCEPTION | 0
C_DPLB_BUS_EXCEPTION | 0
C_DIV_ZERO_EXCEPTION | 0
C_FPU_EXCEPTION | 0
C_FSL_EXCEPTION | 0
C_USE_STACK_PROTECTION | 0
C_PVR | 1
C_PVR_USER1 | 0x03
C_PVR_USER2 | 0x00000000
C_DEBUG_ENABLED | 1
C_NUMBER_OF_PC_BRK | 1
C_NUMBER_OF_RD_ADDR_BRK | 0
C_NUMBER_OF_WR_ADDR_BRK | 0
C_INTERRUPT_IS_EDGE | 0
C_EDGE_IS_POSITIVE | 1
C_RESET_MSR | 0x00000000
C_OPCODE_0x0_ILLEGAL | 0
C_FSL_LINKS | 2
C_FSL_DATA_SIZE | 32
C_USE_EXTENDED_FSL_INSTR | 1
C_M0_AXIS_PROTOCOL | GENERIC
C_S0_AXIS_PROTOCOL | GENERIC
C_M1_AXIS_PROTOCOL | GENERIC
C_S1_AXIS_PROTOCOL | GENERIC
C_M2_AXIS_PROTOCOL | GENERIC
C_S2_AXIS_PROTOCOL | GENERIC
C_M3_AXIS_PROTOCOL | GENERIC
C_S3_AXIS_PROTOCOL | GENERIC
C_M4_AXIS_PROTOCOL | GENERIC
C_S4_AXIS_PROTOCOL | GENERIC
C_M5_AXIS_PROTOCOL | GENERIC
C_S5_AXIS_PROTOCOL | GENERIC
C_M6_AXIS_PROTOCOL | GENERIC
C_S6_AXIS_PROTOCOL | GENERIC
C_M7_AXIS_PROTOCOL | GENERIC
C_S7_AXIS_PROTOCOL | GENERIC
C_M8_AXIS_PROTOCOL | GENERIC
C_S8_AXIS_PROTOCOL | GENERIC
C_M9_AXIS_PROTOCOL | GENERIC
C_S9_AXIS_PROTOCOL | GENERIC
C_M10_AXIS_PROTOCOL | GENERIC
C_S10_AXIS_PROTOCOL | GENERIC
C_M11_AXIS_PROTOCOL | GENERIC
C_S11_AXIS_PROTOCOL | GENERIC
C_M12_AXIS_PROTOCOL | GENERIC
C_S12_AXIS_PROTOCOL | GENERIC
C_M13_AXIS_PROTOCOL | GENERIC
C_S13_AXIS_PROTOCOL | GENERIC
C_M14_AXIS_PROTOCOL | GENERIC |  | Name | Value
C_S14_AXIS_PROTOCOL | GENERIC
C_M15_AXIS_PROTOCOL | GENERIC
C_S15_AXIS_PROTOCOL | GENERIC
C_M0_AXIS_DATA_WIDTH | 32
C_S0_AXIS_DATA_WIDTH | 32
C_M1_AXIS_DATA_WIDTH | 32
C_S1_AXIS_DATA_WIDTH | 32
C_M2_AXIS_DATA_WIDTH | 32
C_S2_AXIS_DATA_WIDTH | 32
C_M3_AXIS_DATA_WIDTH | 32
C_S3_AXIS_DATA_WIDTH | 32
C_M4_AXIS_DATA_WIDTH | 32
C_S4_AXIS_DATA_WIDTH | 32
C_M5_AXIS_DATA_WIDTH | 32
C_S5_AXIS_DATA_WIDTH | 32
C_M6_AXIS_DATA_WIDTH | 32
C_S6_AXIS_DATA_WIDTH | 32
C_M7_AXIS_DATA_WIDTH | 32
C_S7_AXIS_DATA_WIDTH | 32
C_M8_AXIS_DATA_WIDTH | 32
C_S8_AXIS_DATA_WIDTH | 32
C_M9_AXIS_DATA_WIDTH | 32
C_S9_AXIS_DATA_WIDTH | 32
C_M10_AXIS_DATA_WIDTH | 32
C_S10_AXIS_DATA_WIDTH | 32
C_M11_AXIS_DATA_WIDTH | 32
C_S11_AXIS_DATA_WIDTH | 32
C_M12_AXIS_DATA_WIDTH | 32
C_S12_AXIS_DATA_WIDTH | 32
C_M13_AXIS_DATA_WIDTH | 32
C_S13_AXIS_DATA_WIDTH | 32
C_M14_AXIS_DATA_WIDTH | 32
C_S14_AXIS_DATA_WIDTH | 32
C_M15_AXIS_DATA_WIDTH | 32
C_S15_AXIS_DATA_WIDTH | 32
C_ICACHE_BASEADDR | 0x90000000
C_ICACHE_HIGHADDR | 0x9FFFFFFF
C_USE_ICACHE | 1
C_ALLOW_ICACHE_WR | 1
C_ADDR_TAG_BITS | 17
C_CACHE_BYTE_SIZE | 8192
C_ICACHE_USE_FSL | 1
C_ICACHE_LINE_LEN | 4
C_ICACHE_ALWAYS_USED | 1
C_ICACHE_INTERFACE | 0
C_ICACHE_VICTIMS | 0
C_ICACHE_STREAMS | 0
C_ICACHE_FORCE_TAG_LUTRAM | 0
C_ICACHE_DATA_WIDTH | 0
C_M_AXI_IC_SUPPORTS_THREADS | 0
C_M_AXI_IC_THREAD_ID_WIDTH | 1
C_M_AXI_IC_SUPPORTS_READ | 1
C_M_AXI_IC_SUPPORTS_WRITE | 0
C_M_AXI_IC_SUPPORTS_NARROW_BURST | 0
C_M_AXI_IC_DATA_WIDTH | 32
C_M_AXI_IC_ADDR_WIDTH | 32
C_M_AXI_IC_PROTOCOL | AXI4
C_M_AXI_IC_USER_VALUE | 0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS | 1
C_M_AXI_IC_AWUSER_WIDTH | 5
C_M_AXI_IC_ARUSER_WIDTH | 5
C_M_AXI_IC_WUSER_WIDTH | 1
C_M_AXI_IC_RUSER_WIDTH | 1
C_M_AXI_IC_BUSER_WIDTH | 1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING | 2
C_DCACHE_BASEADDR | 0x90000000
C_DCACHE_HIGHADDR | 0x9FFFFFFF
C_USE_DCACHE | 1
C_ALLOW_DCACHE_WR | 1
C_DCACHE_ADDR_TAG | 17
C_DCACHE_BYTE_SIZE | 16384
C_DCACHE_USE_FSL | 1
C_DCACHE_LINE_LEN | 4
C_DCACHE_ALWAYS_USED | 1
C_DCACHE_INTERFACE | 0
C_DCACHE_USE_WRITEBACK | 0
C_DCACHE_VICTIMS | 0
C_DCACHE_FORCE_TAG_LUTRAM | 0
C_DCACHE_DATA_WIDTH | 0
C_M_AXI_DC_SUPPORTS_THREADS | 0
C_M_AXI_DC_THREAD_ID_WIDTH | 1
C_M_AXI_DC_SUPPORTS_READ | 1
C_M_AXI_DC_SUPPORTS_WRITE | 1
C_M_AXI_DC_SUPPORTS_NARROW_BURST | 0
C_M_AXI_DC_DATA_WIDTH | 32
C_M_AXI_DC_ADDR_WIDTH | 32
C_M_AXI_DC_PROTOCOL | AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS | 0
C_M_AXI_DC_USER_VALUE | 0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS | 1
C_M_AXI_DC_AWUSER_WIDTH | 5
C_M_AXI_DC_ARUSER_WIDTH | 5
C_M_AXI_DC_WUSER_WIDTH | 1
C_M_AXI_DC_RUSER_WIDTH | 1
C_M_AXI_DC_BUSER_WIDTH | 1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING | 2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING | 32
C_USE_MMU | 0
C_MMU_DTLB_SIZE | 4
C_MMU_ITLB_SIZE | 2
C_MMU_TLB_ACCESS | 3
C_MMU_ZONES | 16
C_MMU_PRIVILEGED_INSTR | 0
C_USE_INTERRUPT | 0
C_USE_EXT_BRK | 0
C_USE_EXT_NM_BRK | 0
C_USE_BRANCH_TARGET_CACHE | 0
C_BRANCH_TARGET_CACHE_SIZE | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Debuggers | TOP
shared_mdm MicroBlaze Debug Module (MDM) Debug module for MicroBlaze Soft Processor.
IP Specs
Core | Version | Documentation
mdm | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | Debug_SYS_Rst | O | 1 | Debug_SYS_Rst
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
MBDEBUG_0 | INITIATOR | XIL_MBDEBUG3 | shared_mdm_MBDEBUG_0 | microblaze_0
MBDEBUG_1 | INITIATOR | XIL_MBDEBUG3 | shared_mdm_MBDEBUG_1 | microblaze_1
MBDEBUG_2 | INITIATOR | XIL_MBDEBUG3 | shared_mdm_MBDEBUG_2 | microblaze_2
MBDEBUG_3 | INITIATOR | XIL_MBDEBUG3 | shared_mdm_MBDEBUG_3 | microblaze_3
SPLB | SLAVE | PLBV46 | shared_plb | 7 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_JTAG_CHAIN | 2
C_INTERCONNECT | 1
C_BASEADDR | 0x84400000
C_HIGHADDR | 0x8440FFFF
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_P2P | 0
C_SPLB_MID_WIDTH | 3 |  | Name | Value
C_SPLB_NUM_MASTERS | 8
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_SUPPORT_BURSTS | 0
C_MB_DBG_PORTS | 4
C_USE_UART | 1
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_S_AXI_PROTOCOL | AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Busses | TOP
dlmb_0 Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
IP Specs
Core | Version | Documentation
lmb_v10 | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | LMB_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | DLMB
bram_cntlr_0 | SLAVE | SLMB
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_LMB_NUM_SLAVES | 4
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_EXT_RESET_HIGH | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
dlmb_1 Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
IP Specs
Core | Version | Documentation
lmb_v10 | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | LMB_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_1 | MASTER | DLMB
bram_cntlr_1 | SLAVE | SLMB
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_LMB_NUM_SLAVES | 4
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_EXT_RESET_HIGH | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
dlmb_2 Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
IP Specs
Core | Version | Documentation
lmb_v10 | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | LMB_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_2 | MASTER | DLMB
bram_cntlr_2 | SLAVE | SLMB
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_LMB_NUM_SLAVES | 4
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_EXT_RESET_HIGH | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
dlmb_3 Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
IP Specs
Core | Version | Documentation
lmb_v10 | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | LMB_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_3 | MASTER | DLMB
bram_cntlr_3 | SLAVE | SLMB
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_LMB_NUM_SLAVES | 4
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_EXT_RESET_HIGH | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_mb0_to_mutex Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | MFSL0
shared_mutex | SLAVE | SFSL_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_mb0_to_tmr Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | MFSL1
fsl_timer_0 | SLAVE | SFSL_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_mb1_to_mutex Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_1 | MASTER | MFSL0
shared_mutex | SLAVE | SFSL_1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_mb1_to_tmr Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_1 | MASTER | MFSL1
fsl_timer_0 | SLAVE | SFSL_1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_mb2_to_mutex Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_2 | MASTER | MFSL0
shared_mutex | SLAVE | SFSL_2
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_mb2_to_tmr Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_2 | MASTER | MFSL1
fsl_timer_0 | SLAVE | SFSL_2
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_mb3_to_mutex Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_3 | MASTER | MFSL0
shared_mutex | SLAVE | SFSL_3
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_mb3_to_tmr Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_3 | MASTER | MFSL1
fsl_timer_0 | SLAVE | SFSL_3
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_mutex_to_mb0 Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
shared_mutex | MASTER | MFSL_0
microblaze_0 | SLAVE | SFSL0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_mutex_to_mb1 Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
shared_mutex | MASTER | MFSL_1
microblaze_1 | SLAVE | SFSL0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_mutex_to_mb2 Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
shared_mutex | MASTER | MFSL_2
microblaze_2 | SLAVE | SFSL0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_mutex_to_mb3 Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
shared_mutex | MASTER | MFSL_3
microblaze_3 | SLAVE | SFSL0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_tmr_to_mb0 Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
fsl_timer_0 | MASTER | MFSL_0
microblaze_0 | SLAVE | SFSL1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_tmr_to_mb1 Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
fsl_timer_0 | MASTER | MFSL_1
microblaze_1 | SLAVE | SFSL1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_tmr_to_mb2 Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
fsl_timer_0 | MASTER | MFSL_2
microblaze_2 | SLAVE | SFSL1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_tmr_to_mb3 Fast Simplex Link (FSL) Bus Fast Simplex Link (FSL) is a fast uni-directional point to point communication channel
IP Specs
Core | Version | Documentation
fsl_v20 | 2.11.e | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | FSL_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
fsl_timer_0 | MASTER | MFSL_3
microblaze_3 | SLAVE | SFSL1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_EXT_RESET_HIGH | 1
C_ASYNC_CLKS | 0
C_IMPL_STYLE | 0
C_USE_CONTROL | 1
C_FSL_DWIDTH | 32
C_FSL_DEPTH | 16
C_READ_CLOCK_PERIOD | 0 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
ilmb_0 Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
IP Specs
Core | Version | Documentation
lmb_v10 | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | LMB_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | ILMB
bram_cntlr_0 | SLAVE | SLMB_1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_LMB_NUM_SLAVES | 4
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_EXT_RESET_HIGH | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
ilmb_1 Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
IP Specs
Core | Version | Documentation
lmb_v10 | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | LMB_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_1 | MASTER | ILMB
bram_cntlr_1 | SLAVE | SLMB_1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_LMB_NUM_SLAVES | 4
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_EXT_RESET_HIGH | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
ilmb_2 Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
IP Specs
Core | Version | Documentation
lmb_v10 | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | LMB_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_2 | MASTER | ILMB
bram_cntlr_2 | SLAVE | SLMB_1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_LMB_NUM_SLAVES | 4
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_EXT_RESET_HIGH | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
ilmb_3 Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
IP Specs
Core | Version | Documentation
lmb_v10 | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | LMB_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_3 | MASTER | ILMB
bram_cntlr_3 | SLAVE | SLMB_1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_LMB_NUM_SLAVES | 4
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_EXT_RESET_HIGH | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
shared_plb Processor Local Bus (PLB) 4.6 'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'
IP Specs
Core | Version | Documentation
plb_v46 | 1.05.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | PLB_Clk | I | 1 | clk_83_3333MHzPLL0
1 | SYS_Rst | I | 1 | sys_bus_reset
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | DPLB
microblaze_0 | MASTER | IPLB
microblaze_1 | MASTER | DPLB
microblaze_1 | MASTER | IPLB
microblaze_2 | MASTER | DPLB
microblaze_2 | MASTER | IPLB
microblaze_3 | MASTER | DPLB
microblaze_3 | MASTER | IPLB
RS232_Uart_1 | SLAVE | SPLB
shared_mdm | SLAVE | SPLB
kernel_bram_if_cntlr | SLAVE | SPLB
SysACE_CompactFlash | SLAVE | SPLB
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_PLBV46_NUM_MASTERS | 4
C_PLBV46_NUM_SLAVES | 8
C_PLBV46_MID_WIDTH | 2
C_PLBV46_AWIDTH | 32
C_PLBV46_DWIDTH | 64
C_DCR_INTFCE | 0
C_BASEADDR | 0B1111111111
C_HIGHADDR | 0B0000000000
C_DCR_AWIDTH | 10 |  | Name | Value
C_DCR_DWIDTH | 32
C_EXT_RESET_HIGH | 1
C_IRQ_ACTIVE | 1
C_NUM_CLK_PLB2OPB_REARB | 5
C_ADDR_PIPELINING_TYPE | 1
C_FAMILY | virtex5
C_P2P | 0
C_ARB_TYPE | 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Memorys | TOP
kernel_bram Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.
IP Specs
Core | Version | Documentation
bram_block | 1.00.a | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
PORTA | TARGET | XIL_BRAM | kernel_bram_if_cntlr_PORTA | kernel_bram_if_cntlr
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_MEMSIZE | 2048
C_PORT_DWIDTH | 32
C_PORT_AWIDTH | 32
C_NUM_WE | 4
C_FAMILY | virtex2 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
lmb_bram_0 Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.
IP Specs
Core | Version | Documentation
bram_block | 1.00.a | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
PORTA | TARGET | XIL_BRAM | bram_cntlr_0_BRAM_PORT | bram_cntlr_0
PORTB | TARGET | XIL_BRAM | bram_cntlr_0_BRAM_PORT_1 | bram_cntlr_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_MEMSIZE | 2048
C_PORT_DWIDTH | 32
C_PORT_AWIDTH | 32
C_NUM_WE | 4
C_FAMILY | virtex2 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
lmb_bram_1 Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.
IP Specs
Core | Version | Documentation
bram_block | 1.00.a | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
PORTA | TARGET | XIL_BRAM | bram_cntlr_1_BRAM_PORT | bram_cntlr_1
PORTB | TARGET | XIL_BRAM | bram_cntlr_1_BRAM_PORT_1 | bram_cntlr_1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_MEMSIZE | 2048
C_PORT_DWIDTH | 32
C_PORT_AWIDTH | 32
C_NUM_WE | 4
C_FAMILY | virtex2 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
lmb_bram_2 Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.
IP Specs
Core | Version | Documentation
bram_block | 1.00.a | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
PORTA | TARGET | XIL_BRAM | bram_cntlr_2_BRAM_PORT | bram_cntlr_2
PORTB | TARGET | XIL_BRAM | bram_cntlr_2_BRAM_PORT_1 | bram_cntlr_2
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_MEMSIZE | 2048
C_PORT_DWIDTH | 32
C_PORT_AWIDTH | 32
C_NUM_WE | 4
C_FAMILY | virtex2 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
lmb_bram_3 Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.
IP Specs
Core | Version | Documentation
bram_block | 1.00.a | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
PORTA | TARGET | XIL_BRAM | bram_cntlr_3_BRAM_PORT | bram_cntlr_3
PORTB | TARGET | XIL_BRAM | bram_cntlr_3_BRAM_PORT_1 | bram_cntlr_3
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_MEMSIZE | 2048
C_PORT_DWIDTH | 32
C_PORT_AWIDTH | 32
C_NUM_WE | 4
C_FAMILY | virtex2 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Memory Controllers | TOP
DDR2_SDRAM Multi-Port Memory Controller(DDR/DDR2/SDRAM) Multi-port memory controller.
IP Specs
Core | Version | Documentation
mpmc | 6.05.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | MPMC_Clk0 | I | 1 | clk_166_6667MHzPLL0
1 | MPMC_Clk0_DIV2 | I | 1 | clk_83_3333MHzPLL0
2 | MPMC_Clk90 | I | 1 | clk_166_6667MHz90PLL0
3 | MPMC_Clk_200MHz | I | 1 | clk_200_0000MHz
4 | MPMC_Rst | I | 1 | sys_periph_reset
5 | DDR2_Clk | O | 1 | fpga_0_DDR2_SDRAM_DDR2_Clk_pin
6 | DDR2_Clk_n | O | 1 | fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin
7 | DDR2_CE | O | 1 | fpga_0_DDR2_SDRAM_DDR2_CE_pin
8 | DDR2_CS_n | O | 1 | fpga_0_DDR2_SDRAM_DDR2_CS_n_pin
9 | DDR2_ODT | O | 1 | fpga_0_DDR2_SDRAM_DDR2_ODT_pin
10 | DDR2_RAS_n | O | 1 | fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin
11 | DDR2_CAS_n | O | 1 | fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin
12 | DDR2_WE_n | O | 1 | fpga_0_DDR2_SDRAM_DDR2_WE_n_pin
13 | DDR2_BankAddr | O | 1 | fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin
14 | DDR2_Addr | O | 1 | fpga_0_DDR2_SDRAM_DDR2_Addr_pin
15 | DDR2_DQ | IO | 1 | fpga_0_DDR2_SDRAM_DDR2_DQ_pin
16 | DDR2_DM | O | 1 | fpga_0_DDR2_SDRAM_DDR2_DM_pin
17 | DDR2_DQS | IO | 1 | fpga_0_DDR2_SDRAM_DDR2_DQS_pin
18 | DDR2_DQS_n | IO | 1 | fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
XCL2 | TARGET | XIL_MEMORY_CHANNEL | microblaze_1_IXCL | microblaze_1
XCL0 | TARGET | XIL_MEMORY_CHANNEL | microblaze_0_IXCL | microblaze_0
XCL4 | TARGET | XIL_MEMORY_CHANNEL | microblaze_2_IXCL | microblaze_2
XCL6 | TARGET | XIL_MEMORY_CHANNEL | microblaze_3_IXCL | microblaze_3
XCL1 | TARGET | XIL_MEMORY_CHANNEL | microblaze_0_DXCL | microblaze_0
XCL3 | TARGET | XIL_MEMORY_CHANNEL | microblaze_1_DXCL | microblaze_1
XCL5 | TARGET | XIL_MEMORY_CHANNEL | microblaze_2_DXCL | microblaze_2
XCL7 | TARGET | XIL_MEMORY_CHANNEL | microblaze_3_DXCL | microblaze_3
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex5
C_BASEFAMILY | virtex5
C_SUBFAMILY | fx
C_DEVICE | 5vlx50t
C_PACKAGE | ff1136
C_SPEEDGRADE | -1
C_SPEEDGRADE_INT | 1
C_NUM_PORTS | 8
C_PORT_CONFIG | 1
C_ALL_PIMS_SHARE_ADDRESSES | 1
C_MPMC_BASEADDR | 0x90000000
C_MPMC_HIGHADDR | 0x9FFFFFFF
C_MPMC_SW_BASEADDR | 0xFFFFFFFF
C_MPMC_SW_HIGHADDR | 0x00000000
C_SDMA_CTRL_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL_HIGHADDR | 0x00000000
C_MPMC_CTRL_BASEADDR | 0xFFFFFFFF
C_MPMC_CTRL_HIGHADDR | 0x00000000
C_MPMC_CTRL_AWIDTH | 32
C_MPMC_CTRL_DWIDTH | 64
C_MPMC_CTRL_NATIVE_DWIDTH | 32
C_MPMC_CTRL_NUM_MASTERS | 1
C_MPMC_CTRL_MID_WIDTH | 1
C_MPMC_CTRL_P2P | 1
C_MPMC_CTRL_SUPPORT_BURSTS | 0
C_MPMC_CTRL_SMALLEST_MASTER | 32
C_NUM_IDELAYCTRL | 3
C_IDELAYCTRL_LOC | IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1
C_IODELAY_GRP | NOT_SET
C_MCB_LOC | NOT_SET
C_MMCM_EXT_LOC | NOT_SET
C_MMCM_INT_LOC | NOT_SET
C_MAX_REQ_ALLOWED | 1
C_ARB_PIPELINE | 1
C_WR_DATAPATH_TML_PIPELINE | 1
C_RD_DATAPATH_TML_MAX_FANOUT | 0
C_ARB_USE_DEFAULT | 0
C_ARB0_ALGO | ROUND_ROBIN
C_ARB0_NUM_SLOTS | 8
C_ARB0_SLOT0 | 01234567
C_ARB0_SLOT1 | 12345670
C_ARB0_SLOT2 | 23456701
C_ARB0_SLOT3 | 34567012
C_ARB0_SLOT4 | 45670123
C_ARB0_SLOT5 | 56701234
C_ARB0_SLOT6 | 67012345
C_ARB0_SLOT7 | 70123456
C_ARB0_SLOT8 | 01234567
C_ARB0_SLOT9 | 12345670
C_ARB0_SLOT10 | 23456701
C_ARB0_SLOT11 | 34567012
C_ARB0_SLOT12 | 45670123
C_ARB0_SLOT13 | 56701234
C_ARB0_SLOT14 | 67012345
C_ARB0_SLOT15 | 70123456
C_PM_ENABLE | 0
C_PM_DC_WIDTH | 48
C_PM_GC_CNTR | 1
C_PM_GC_WIDTH | 48
C_PM_SHIFT_CNT_BY | 1
C_SKIP_SIM_INIT_DELAY | 0
C_USE_MIG_S3_PHY | 0
C_USE_MIG_V4_PHY | 0
C_USE_MIG_V5_PHY | 0
C_USE_MIG_V6_PHY | 0
C_USE_MCB_S6_PHY | 0
C_USE_STATIC_PHY | 0
C_STATIC_PHY_RDDATA_CLK_SEL | 0
C_STATIC_PHY_RDDATA_SWAP_RISE | 0
C_STATIC_PHY_RDEN_DELAY | 5
C_DEBUG_REG_ENABLE | 0
C_SPECIAL_BOARD | NONE
C_USE_MIG_FLOW | 0
C_MEM_ADDR_ORDER | BANK_ROW_COLUMN
C_MEM_CALIBRATION_MODE | 1
C_MEM_CALIBRATION_DELAY | HALF
C_MEM_CALIBRATION_SOFT_IP | FALSE
C_MEM_CALIBRATION_BYPASS | NO
C_MPMC_MCB_DRP_CLK_PRESENT | 0
C_MEM_SKIP_IN_TERM_CAL | 1
C_MEM_SKIP_DYNAMIC_CAL | 1
C_MEM_SKIP_DYN_IN_TERM | 1
C_MEM_INCDEC_THRESHOLD | 0x02
C_MEM_CHECK_MAX_INDELAY | 0
C_MEM_CHECK_MAX_TAP_REG | 0
C_MEM_TZQINIT_MAXCNT | 528
C_MPMC_CLK_MEM_2X_PERIOD_PS | 1
C_MCB_USE_EXTERNAL_BUFPLL | 0
C_MCB_LDQSP_TAP_DELAY_VAL | 0
C_MCB_UDQSP_TAP_DELAY_VAL | 0
C_MCB_LDQSN_TAP_DELAY_VAL | 0
C_MCB_UDQSN_TAP_DELAY_VAL | 0
C_MCB_DQ0_TAP_DELAY_VAL | 0
C_MCB_DQ1_TAP_DELAY_VAL | 0
C_MCB_DQ2_TAP_DELAY_VAL | 0
C_MCB_DQ3_TAP_DELAY_VAL | 0
C_MCB_DQ4_TAP_DELAY_VAL | 0
C_MCB_DQ5_TAP_DELAY_VAL | 0
C_MCB_DQ6_TAP_DELAY_VAL | 0
C_MCB_DQ7_TAP_DELAY_VAL | 0
C_MCB_DQ8_TAP_DELAY_VAL | 0
C_MCB_DQ9_TAP_DELAY_VAL | 0
C_MCB_DQ10_TAP_DELAY_VAL | 0
C_MCB_DQ11_TAP_DELAY_VAL | 0
C_MCB_DQ12_TAP_DELAY_VAL | 0
C_MCB_DQ13_TAP_DELAY_VAL | 0
C_MCB_DQ14_TAP_DELAY_VAL | 0
C_MCB_DQ15_TAP_DELAY_VAL | 0
C_MCB_RZQ_LOC | NOT_SET
C_MCB_ZIO_LOC | NOT_SET
C_MEM_TYPE | DDR2
C_MEM_PARTNO | mt4htf3264h-53e
C_MEM_PART_DATA_DEPTH | 16
C_MEM_PART_DATA_WIDTH | 8
C_MEM_PART_NUM_BANK_BITS | 2
C_MEM_PART_NUM_ROW_BITS | 13
C_MEM_PART_NUM_COL_BITS | 9
C_MEM_PART_TRAS | 0
C_MEM_PART_TRASMAX | 0
C_MEM_PART_TRC | 0
C_MEM_PART_TRCD | 0
C_MEM_PART_TDQSS | 1
C_MEM_PART_TWR | 0
C_MEM_PART_TRP | 0
C_MEM_PART_TMRD | 4
C_MEM_PART_TRRD | 0
C_MEM_PART_TRFC | 0
C_MEM_PART_TREFI | 0
C_MEM_PART_TAL | 0
C_MEM_PART_TCCD | 0
C_MEM_PART_TWTR | 0
C_MEM_PART_TRTP | 7500
C_MEM_PART_TZQINIT | 512
C_MEM_PART_TZQCS | 64
C_MEM_PART_TPRDI | 1000000
C_MEM_PART_TZQI | 128000000
C_MEM_PART_CAS_A_FMAX | 0
C_MEM_PART_CAS_A | 0
C_MEM_PART_CAS_B_FMAX | 0
C_MEM_PART_CAS_B | 0
C_MEM_PART_CAS_C_FMAX | 0
C_MEM_PART_CAS_C | 0
C_MEM_PART_CAS_D_FMAX | 0
C_MEM_PART_CAS_D | 0
C_MPMC_CLK0_PERIOD_PS | 1
C_MPMC_CLK_MEM_PERIOD_PS | 1
C_MEM_CAS_LATENCY | 3
C_MEM_ODT_TYPE | 1
C_MEM_REDUCED_DRV | 0
C_MEM_REG_DIMM | 0
C_MEM_CLK_WIDTH | 2
C_MEM_ODT_WIDTH | 2
C_MEM_CE_WIDTH | 2
C_MEM_CS_N_WIDTH | 2
C_MEM_ADDR_WIDTH | 13
C_MEM_BANKADDR_WIDTH | 2
C_MEM_DATA_WIDTH | 64
C_MEM_BITS_DATA_PER_DQS | 8
C_MEM_DM_WIDTH | 8
C_MEM_DQS_WIDTH | 8
C_MEM_NUM_DIMMS | 1
C_MEM_NUM_RANKS | 1
C_MEM_DQS_IO_COL | 0x000000000000000000
C_MEM_DQ_IO_MS | 0x000000000000000000
C_DDR2_DQSN_ENABLE | 1
C_INCLUDE_ECC_SUPPORT | 0
C_ECC_DEFAULT_ON | 1
C_INCLUDE_ECC_TEST | 0
C_ECC_SEC_THRESHOLD | 1
C_ECC_DEC_THRESHOLD | 1
C_ECC_PEC_THRESHOLD | 1
C_ECC_DATA_WIDTH | 0
C_ECC_DM_WIDTH | 0
C_ECC_DQS_WIDTH | 0
C_MEM_PA_SR | 0
C_MEM_CAS_WR_LATENCY | 5
C_MEM_AUTO_SR | ENABLED
C_MEM_HIGH_TEMP_SR | NORMAL
C_MEM_DYNAMIC_WRITE_ODT | OFF
C_MEM_WRLVL | 1
C_IDELAY_CLK_FREQ | DEFAULT
C_MEM_PHASE_DETECT | DEFAULT
C_MEM_IBUF_LPWR_MODE | DEFAULT
C_MEM_IODELAY_HP_MODE | DEFAULT
C_MEM_SIM_INIT_OPTION | DEFAULT
C_MEM_SIM_CAL_OPTION | DEFAULT
C_MEM_CAL_WIDTH | DEFAULT
C_MEM_NDQS_COL0 | 0
C_MEM_NDQS_COL1 | 0
C_MEM_NDQS_COL2 | 0
C_MEM_NDQS_COL3 | 0
C_MEM_DQS_LOC_COL0 | 0x000000000000000000000000000000000000
C_MEM_DQS_LOC_COL1 | 0x000000000000000000000000000000000000
C_MEM_DQS_LOC_COL2 | 0x000000000000000000000000000000000000
C_MEM_DQS_LOC_COL3 | 0x000000000000000000000000000000000000
C_MAINT_PRESCALER_PERIOD | 200000
C_TBY4TAPVALUE | 9999
C_PIM0_BASEADDR | 0xFFFFFFFF
C_PIM0_HIGHADDR | 0x00000000
C_PIM0_OFFSET | 0x00000000
C_PIM0_DATA_WIDTH | 64
C_PIM0_BASETYPE | 1
C_PIM0_SUBTYPE | PLB
C_XCL0_LINESIZE | 4
C_XCL0_WRITEXFER | 1
C_XCL0_PIPE_STAGES | 2
C_XCL0_B_IN_USE | 0
C_PIM0_B_SUBTYPE | INACTIVE
C_XCL0_B_LINESIZE | 4
C_XCL0_B_WRITEXFER | 1
C_SPLB0_AWIDTH | 32
C_SPLB0_DWIDTH | 64
C_SPLB0_NATIVE_DWIDTH | 64
C_SPLB0_NUM_MASTERS | 1
C_SPLB0_MID_WIDTH | 1
C_SPLB0_P2P | 1
C_SPLB0_SUPPORT_BURSTS | 0
C_SPLB0_SMALLEST_MASTER | 32
C_SDMA_CTRL0_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL0_HIGHADDR | 0x00000000
C_SDMA_CTRL0_AWIDTH | 32
C_SDMA_CTRL0_DWIDTH | 64
C_SDMA_CTRL0_NATIVE_DWIDTH | 32
C_SDMA_CTRL0_NUM_MASTERS | 1
C_SDMA_CTRL0_MID_WIDTH | 1
C_SDMA_CTRL0_P2P | 1
C_SDMA_CTRL0_SUPPORT_BURSTS | 0
C_SDMA_CTRL0_SMALLEST_MASTER | 32
C_SDMA0_COMPLETED_ERR_TX | 1
C_SDMA0_COMPLETED_ERR_RX | 1
C_SDMA0_PRESCALAR | 1023
C_SDMA0_PI2LL_CLK_RATIO | 1
C_PPC440MC0_BURST_LENGTH | 4
C_PPC440MC0_PIPE_STAGES | 1
C_VFBC0_CMD_FIFO_DEPTH | 32
C_VFBC0_CMD_AFULL_COUNT | 3
C_VFBC0_RDWD_DATA_WIDTH | 32
C_VFBC0_RDWD_FIFO_DEPTH | 1024
C_VFBC0_RD_AEMPTY_WD_AFULL_COUNT | 3
C_PI0_RD_FIFO_TYPE | SRL
C_PI0_WR_FIFO_TYPE | SRL
C_PI0_ADDRACK_PIPELINE | 1
C_PI0_RD_FIFO_APP_PIPELINE | 1
C_PI0_RD_FIFO_MEM_PIPELINE | 1
C_PI0_WR_FIFO_APP_PIPELINE | 1
C_PI0_WR_FIFO_MEM_PIPELINE | 1
C_PI0_PM_USED | 1
C_PI0_PM_DC_CNTR | 1
C_PIM1_BASEADDR | 0xFFFFFFFF
C_PIM1_HIGHADDR | 0x00000000
C_PIM1_OFFSET | 0x00000000
C_PIM1_DATA_WIDTH | 64
C_PIM1_BASETYPE | 1
C_PIM1_SUBTYPE | INACTIVE
C_XCL1_LINESIZE | 4
C_XCL1_WRITEXFER | 1
C_XCL1_PIPE_STAGES | 2
C_XCL1_B_IN_USE | 0
C_PIM1_B_SUBTYPE | INACTIVE
C_XCL1_B_LINESIZE | 4
C_XCL1_B_WRITEXFER | 1
C_SPLB1_AWIDTH | 32
C_SPLB1_DWIDTH | 64
C_SPLB1_NATIVE_DWIDTH | 64
C_SPLB1_NUM_MASTERS | 1
C_SPLB1_MID_WIDTH | 1
C_SPLB1_P2P | 1
C_SPLB1_SUPPORT_BURSTS | 0
C_SPLB1_SMALLEST_MASTER | 32
C_SDMA_CTRL1_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL1_HIGHADDR | 0x00000000
C_SDMA_CTRL1_AWIDTH | 32
C_SDMA_CTRL1_DWIDTH | 64
C_SDMA_CTRL1_NATIVE_DWIDTH | 32
C_SDMA_CTRL1_NUM_MASTERS | 1
C_SDMA_CTRL1_MID_WIDTH | 1
C_SDMA_CTRL1_P2P | 1
C_SDMA_CTRL1_SUPPORT_BURSTS | 0
C_SDMA_CTRL1_SMALLEST_MASTER | 32
C_SDMA1_COMPLETED_ERR_TX | 1
C_SDMA1_COMPLETED_ERR_RX | 1
C_SDMA1_PRESCALAR | 1023
C_SDMA1_PI2LL_CLK_RATIO | 1
C_PPC440MC1_BURST_LENGTH | 4
C_PPC440MC1_PIPE_STAGES | 1
C_VFBC1_CMD_FIFO_DEPTH | 32
C_VFBC1_CMD_AFULL_COUNT | 3
C_VFBC1_RDWD_DATA_WIDTH | 32
C_VFBC1_RDWD_FIFO_DEPTH | 1024
C_VFBC1_RD_AEMPTY_WD_AFULL_COUNT | 3
C_PI1_RD_FIFO_TYPE | SRL
C_PI1_WR_FIFO_TYPE | SRL
C_PI1_ADDRACK_PIPELINE | 1
C_PI1_RD_FIFO_APP_PIPELINE | 1
C_PI1_RD_FIFO_MEM_PIPELINE | 1
C_PI1_WR_FIFO_APP_PIPELINE | 1
C_PI1_WR_FIFO_MEM_PIPELINE | 1
C_PI1_PM_USED | 1
C_PI1_PM_DC_CNTR | 1
C_PIM2_BASEADDR | 0xFFFFFFFF
C_PIM2_HIGHADDR | 0x00000000
C_PIM2_OFFSET | 0x00000000
C_PIM2_DATA_WIDTH | 64
C_PIM2_BASETYPE | 1
C_PIM2_SUBTYPE | INACTIVE
C_XCL2_LINESIZE | 4
C_XCL2_WRITEXFER | 1
C_XCL2_PIPE_STAGES | 2
C_XCL2_B_IN_USE | 0
C_PIM2_B_SUBTYPE | INACTIVE
C_XCL2_B_LINESIZE | 4
C_XCL2_B_WRITEXFER | 1
C_SPLB2_AWIDTH | 32
C_SPLB2_DWIDTH | 64
C_SPLB2_NATIVE_DWIDTH | 64
C_SPLB2_NUM_MASTERS | 1
C_SPLB2_MID_WIDTH | 1
C_SPLB2_P2P | 1
C_SPLB2_SUPPORT_BURSTS | 0
C_SPLB2_SMALLEST_MASTER | 32
C_SDMA_CTRL2_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL2_HIGHADDR | 0x00000000
C_SDMA_CTRL2_AWIDTH | 32
C_SDMA_CTRL2_DWIDTH | 64
C_SDMA_CTRL2_NATIVE_DWIDTH | 32
C_SDMA_CTRL2_NUM_MASTERS | 1
C_SDMA_CTRL2_MID_WIDTH | 1
C_SDMA_CTRL2_P2P | 1
C_SDMA_CTRL2_SUPPORT_BURSTS | 0
C_SDMA_CTRL2_SMALLEST_MASTER | 32
C_SDMA2_COMPLETED_ERR_TX | 1
C_SDMA2_COMPLETED_ERR_RX | 1
C_SDMA2_PRESCALAR | 1023
C_SDMA2_PI2LL_CLK_RATIO | 1
C_PPC440MC2_BURST_LENGTH | 4
C_PPC440MC2_PIPE_STAGES | 1
C_VFBC2_CMD_FIFO_DEPTH | 32
C_VFBC2_CMD_AFULL_COUNT | 3
C_VFBC2_RDWD_DATA_WIDTH | 32
C_VFBC2_RDWD_FIFO_DEPTH | 1024
C_VFBC2_RD_AEMPTY_WD_AFULL_COUNT | 3
C_PI2_RD_FIFO_TYPE | SRL
C_PI2_WR_FIFO_TYPE | SRL
C_PI2_ADDRACK_PIPELINE | 1
C_PI2_RD_FIFO_APP_PIPELINE | 1
C_PI2_RD_FIFO_MEM_PIPELINE | 1
C_PI2_WR_FIFO_APP_PIPELINE | 1
C_PI2_WR_FIFO_MEM_PIPELINE | 1
C_PI2_PM_USED | 1
C_PI2_PM_DC_CNTR | 1
C_PIM3_BASEADDR | 0xFFFFFFFF
C_PIM3_HIGHADDR | 0x00000000
C_PIM3_OFFSET | 0x00000000
C_PIM3_DATA_WIDTH | 64
C_PIM3_BASETYPE | 1
C_PIM3_SUBTYPE | INACTIVE
C_XCL3_LINESIZE | 4
C_XCL3_WRITEXFER | 1
C_XCL3_PIPE_STAGES | 2
C_XCL3_B_IN_USE | 0
C_PIM3_B_SUBTYPE | INACTIVE
C_XCL3_B_LINESIZE | 4
C_XCL3_B_WRITEXFER | 1
C_SPLB3_AWIDTH | 32
C_SPLB3_DWIDTH | 64
C_SPLB3_NATIVE_DWIDTH | 64
C_SPLB3_NUM_MASTERS | 1
C_SPLB3_MID_WIDTH | 1
C_SPLB3_P2P | 1
C_SPLB3_SUPPORT_BURSTS | 0
C_SPLB3_SMALLEST_MASTER | 32
C_SDMA_CTRL3_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL3_HIGHADDR | 0x00000000
C_SDMA_CTRL3_AWIDTH | 32
C_SDMA_CTRL3_DWIDTH | 64
C_SDMA_CTRL3_NATIVE_DWIDTH | 32
C_SDMA_CTRL3_NUM_MASTERS | 1
C_SDMA_CTRL3_MID_WIDTH | 1
C_SDMA_CTRL3_P2P | 1
C_SDMA_CTRL3_SUPPORT_BURSTS | 0
C_SDMA_CTRL3_SMALLEST_MASTER | 32
C_SDMA3_COMPLETED_ERR_TX | 1
C_SDMA3_COMPLETED_ERR_RX | 1
C_SDMA3_PRESCALAR | 1023
C_SDMA3_PI2LL_CLK_RATIO | 1
C_PPC440MC3_BURST_LENGTH | 4
C_PPC440MC3_PIPE_STAGES | 1
C_VFBC3_CMD_FIFO_DEPTH | 32
C_VFBC3_CMD_AFULL_COUNT | 3
C_VFBC3_RDWD_DATA_WIDTH | 32
C_VFBC3_RDWD_FIFO_DEPTH | 1024
C_VFBC3_RD_AEMPTY_WD_AFULL_COUNT | 3
C_PI3_RD_FIFO_TYPE | SRL
C_PI3_WR_FIFO_TYPE | SRL
C_PI3_ADDRACK_PIPELINE | 1
C_PI3_RD_FIFO_APP_PIPELINE | 1
C_PI3_RD_FIFO_MEM_PIPELINE | 1
C_PI3_WR_FIFO_APP_PIPELINE | 1
C_PI3_WR_FIFO_MEM_PIPELINE | 1
C_PI3_PM_USED | 1
C_PI3_PM_DC_CNTR | 1
C_PIM4_BASEADDR | 0xFFFFFFFF
C_PIM4_HIGHADDR | 0x00000000
C_PIM4_OFFSET | 0x00000000 |  | Name | Value
C_PIM4_DATA_WIDTH | 64
C_PIM4_BASETYPE | 1
C_PIM4_SUBTYPE | INACTIVE
C_XCL4_LINESIZE | 4
C_XCL4_WRITEXFER | 1
C_XCL4_PIPE_STAGES | 2
C_XCL4_B_IN_USE | 0
C_PIM4_B_SUBTYPE | INACTIVE
C_XCL4_B_LINESIZE | 4
C_XCL4_B_WRITEXFER | 1
C_SPLB4_AWIDTH | 32
C_SPLB4_DWIDTH | 64
C_SPLB4_NATIVE_DWIDTH | 64
C_SPLB4_NUM_MASTERS | 1
C_SPLB4_MID_WIDTH | 1
C_SPLB4_P2P | 1
C_SPLB4_SUPPORT_BURSTS | 0
C_SPLB4_SMALLEST_MASTER | 32
C_SDMA_CTRL4_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL4_HIGHADDR | 0x00000000
C_SDMA_CTRL4_AWIDTH | 32
C_SDMA_CTRL4_DWIDTH | 64
C_SDMA_CTRL4_NATIVE_DWIDTH | 32
C_SDMA_CTRL4_NUM_MASTERS | 1
C_SDMA_CTRL4_MID_WIDTH | 1
C_SDMA_CTRL4_P2P | 1
C_SDMA_CTRL4_SUPPORT_BURSTS | 0
C_SDMA_CTRL4_SMALLEST_MASTER | 32
C_SDMA4_COMPLETED_ERR_TX | 1
C_SDMA4_COMPLETED_ERR_RX | 1
C_SDMA4_PRESCALAR | 1023
C_SDMA4_PI2LL_CLK_RATIO | 1
C_PPC440MC4_BURST_LENGTH | 4
C_PPC440MC4_PIPE_STAGES | 1
C_VFBC4_CMD_FIFO_DEPTH | 32
C_VFBC4_CMD_AFULL_COUNT | 3
C_VFBC4_RDWD_DATA_WIDTH | 32
C_VFBC4_RDWD_FIFO_DEPTH | 1024
C_VFBC4_RD_AEMPTY_WD_AFULL_COUNT | 3
C_PI4_RD_FIFO_TYPE | SRL
C_PI4_WR_FIFO_TYPE | SRL
C_PI4_ADDRACK_PIPELINE | 1
C_PI4_RD_FIFO_APP_PIPELINE | 1
C_PI4_RD_FIFO_MEM_PIPELINE | 1
C_PI4_WR_FIFO_APP_PIPELINE | 1
C_PI4_WR_FIFO_MEM_PIPELINE | 1
C_PI4_PM_USED | 1
C_PI4_PM_DC_CNTR | 1
C_PIM5_BASEADDR | 0xFFFFFFFF
C_PIM5_HIGHADDR | 0x00000000
C_PIM5_OFFSET | 0x00000000
C_PIM5_DATA_WIDTH | 64
C_PIM5_BASETYPE | 1
C_PIM5_SUBTYPE | INACTIVE
C_XCL5_LINESIZE | 4
C_XCL5_WRITEXFER | 1
C_XCL5_PIPE_STAGES | 2
C_XCL5_B_IN_USE | 0
C_PIM5_B_SUBTYPE | INACTIVE
C_XCL5_B_LINESIZE | 4
C_XCL5_B_WRITEXFER | 1
C_SPLB5_AWIDTH | 32
C_SPLB5_DWIDTH | 64
C_SPLB5_NATIVE_DWIDTH | 64
C_SPLB5_NUM_MASTERS | 1
C_SPLB5_MID_WIDTH | 1
C_SPLB5_P2P | 1
C_SPLB5_SUPPORT_BURSTS | 0
C_SPLB5_SMALLEST_MASTER | 32
C_SDMA_CTRL5_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL5_HIGHADDR | 0x00000000
C_SDMA_CTRL5_AWIDTH | 32
C_SDMA_CTRL5_DWIDTH | 64
C_SDMA_CTRL5_NATIVE_DWIDTH | 32
C_SDMA_CTRL5_NUM_MASTERS | 1
C_SDMA_CTRL5_MID_WIDTH | 1
C_SDMA_CTRL5_P2P | 1
C_SDMA_CTRL5_SUPPORT_BURSTS | 0
C_SDMA_CTRL5_SMALLEST_MASTER | 32
C_SDMA5_COMPLETED_ERR_TX | 1
C_SDMA5_COMPLETED_ERR_RX | 1
C_SDMA5_PRESCALAR | 1023
C_SDMA5_PI2LL_CLK_RATIO | 1
C_PPC440MC5_BURST_LENGTH | 4
C_PPC440MC5_PIPE_STAGES | 1
C_VFBC5_CMD_FIFO_DEPTH | 32
C_VFBC5_CMD_AFULL_COUNT | 3
C_VFBC5_RDWD_DATA_WIDTH | 32
C_VFBC5_RDWD_FIFO_DEPTH | 1024
C_VFBC5_RD_AEMPTY_WD_AFULL_COUNT | 3
C_PI5_RD_FIFO_TYPE | SRL
C_PI5_WR_FIFO_TYPE | SRL
C_PI5_ADDRACK_PIPELINE | 1
C_PI5_RD_FIFO_APP_PIPELINE | 1
C_PI5_RD_FIFO_MEM_PIPELINE | 1
C_PI5_WR_FIFO_APP_PIPELINE | 1
C_PI5_WR_FIFO_MEM_PIPELINE | 1
C_PI5_PM_USED | 1
C_PI5_PM_DC_CNTR | 1
C_PIM6_BASEADDR | 0xFFFFFFFF
C_PIM6_HIGHADDR | 0x00000000
C_PIM6_OFFSET | 0x00000000
C_PIM6_DATA_WIDTH | 64
C_PIM6_BASETYPE | 1
C_PIM6_SUBTYPE | INACTIVE
C_XCL6_LINESIZE | 4
C_XCL6_WRITEXFER | 1
C_XCL6_PIPE_STAGES | 2
C_XCL6_B_IN_USE | 0
C_PIM6_B_SUBTYPE | INACTIVE
C_XCL6_B_LINESIZE | 4
C_XCL6_B_WRITEXFER | 1
C_SPLB6_AWIDTH | 32
C_SPLB6_DWIDTH | 64
C_SPLB6_NATIVE_DWIDTH | 64
C_SPLB6_NUM_MASTERS | 1
C_SPLB6_MID_WIDTH | 1
C_SPLB6_P2P | 1
C_SPLB6_SUPPORT_BURSTS | 0
C_SPLB6_SMALLEST_MASTER | 32
C_SDMA_CTRL6_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL6_HIGHADDR | 0x00000000
C_SDMA_CTRL6_AWIDTH | 32
C_SDMA_CTRL6_DWIDTH | 64
C_SDMA_CTRL6_NATIVE_DWIDTH | 32
C_SDMA_CTRL6_NUM_MASTERS | 1
C_SDMA_CTRL6_MID_WIDTH | 1
C_SDMA_CTRL6_P2P | 1
C_SDMA_CTRL6_SUPPORT_BURSTS | 0
C_SDMA_CTRL6_SMALLEST_MASTER | 32
C_SDMA6_COMPLETED_ERR_TX | 1
C_SDMA6_COMPLETED_ERR_RX | 1
C_SDMA6_PRESCALAR | 1023
C_SDMA6_PI2LL_CLK_RATIO | 1
C_PPC440MC6_BURST_LENGTH | 4
C_PPC440MC6_PIPE_STAGES | 1
C_VFBC6_CMD_FIFO_DEPTH | 32
C_VFBC6_CMD_AFULL_COUNT | 3
C_VFBC6_RDWD_DATA_WIDTH | 32
C_VFBC6_RDWD_FIFO_DEPTH | 1024
C_VFBC6_RD_AEMPTY_WD_AFULL_COUNT | 3
C_PI6_RD_FIFO_TYPE | SRL
C_PI6_WR_FIFO_TYPE | SRL
C_PI6_ADDRACK_PIPELINE | 1
C_PI6_RD_FIFO_APP_PIPELINE | 1
C_PI6_RD_FIFO_MEM_PIPELINE | 1
C_PI6_WR_FIFO_APP_PIPELINE | 1
C_PI6_WR_FIFO_MEM_PIPELINE | 1
C_PI6_PM_USED | 1
C_PI6_PM_DC_CNTR | 1
C_PIM7_BASEADDR | 0xFFFFFFFF
C_PIM7_HIGHADDR | 0x00000000
C_PIM7_OFFSET | 0x00000000
C_PIM7_DATA_WIDTH | 64
C_PIM7_BASETYPE | 1
C_PIM7_SUBTYPE | INACTIVE
C_XCL7_LINESIZE | 4
C_XCL7_WRITEXFER | 1
C_XCL7_PIPE_STAGES | 2
C_XCL7_B_IN_USE | 0
C_PIM7_B_SUBTYPE | INACTIVE
C_XCL7_B_LINESIZE | 4
C_XCL7_B_WRITEXFER | 1
C_SPLB7_AWIDTH | 32
C_SPLB7_DWIDTH | 64
C_SPLB7_NATIVE_DWIDTH | 64
C_SPLB7_NUM_MASTERS | 1
C_SPLB7_MID_WIDTH | 1
C_SPLB7_P2P | 1
C_SPLB7_SUPPORT_BURSTS | 0
C_SPLB7_SMALLEST_MASTER | 32
C_SDMA_CTRL7_BASEADDR | 0xFFFFFFFF
C_SDMA_CTRL7_HIGHADDR | 0x00000000
C_SDMA_CTRL7_AWIDTH | 32
C_SDMA_CTRL7_DWIDTH | 64
C_SDMA_CTRL7_NATIVE_DWIDTH | 32
C_SDMA_CTRL7_NUM_MASTERS | 1
C_SDMA_CTRL7_MID_WIDTH | 1
C_SDMA_CTRL7_P2P | 1
C_SDMA_CTRL7_SUPPORT_BURSTS | 0
C_SDMA_CTRL7_SMALLEST_MASTER | 32
C_SDMA7_COMPLETED_ERR_TX | 1
C_SDMA7_COMPLETED_ERR_RX | 1
C_SDMA7_PRESCALAR | 1023
C_SDMA7_PI2LL_CLK_RATIO | 1
C_PPC440MC7_BURST_LENGTH | 4
C_PPC440MC7_PIPE_STAGES | 1
C_VFBC7_CMD_FIFO_DEPTH | 32
C_VFBC7_CMD_AFULL_COUNT | 3
C_VFBC7_RDWD_DATA_WIDTH | 32
C_VFBC7_RDWD_FIFO_DEPTH | 1024
C_VFBC7_RD_AEMPTY_WD_AFULL_COUNT | 3
C_PI7_RD_FIFO_TYPE | SRL
C_PI7_WR_FIFO_TYPE | SRL
C_PI7_ADDRACK_PIPELINE | 1
C_PI7_RD_FIFO_APP_PIPELINE | 1
C_PI7_RD_FIFO_MEM_PIPELINE | 1
C_PI7_WR_FIFO_APP_PIPELINE | 1
C_PI7_WR_FIFO_MEM_PIPELINE | 1
C_PI7_PM_USED | 1
C_PI7_PM_DC_CNTR | 1
C_WR_TRAINING_PORT | 0
C_ARB_BRAM_INIT_00 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000
C_ARB_BRAM_INIT_01 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_BRAM_INIT_02 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000
C_ARB_BRAM_INIT_03 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_BRAM_INIT_04 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111010001000011000000001111111111110010000110100000000011111111111100001101000100000000111111111111011010001000
C_ARB_BRAM_INIT_05 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_ARB_BRAM_INIT_06 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111011010001000000000001111111111110110100010000000000011111111111101101000100000000000111111111111011010001000
C_ARB_BRAM_INIT_07 | 0b0000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111000000001111111111111111111111110000000011111111111111111111111100000000111111111111111111111111
C_NCK_PER_CLK | 1
C_TWR | 0
C_CTRL_COMPLETE_INDEX | 0
C_CTRL_IS_WRITE_INDEX | 0
C_CTRL_PHYIF_RAS_N_INDEX | 0
C_CTRL_PHYIF_CAS_N_INDEX | 0
C_CTRL_PHYIF_WE_N_INDEX | 0
C_CTRL_RMW_INDEX | 0
C_CTRL_SKIP_0_INDEX | 0
C_CTRL_PHYIF_DQS_O_INDEX | 0
C_CTRL_SKIP_1_INDEX | 0
C_CTRL_DP_RDFIFO_PUSH_INDEX | 0
C_CTRL_SKIP_2_INDEX | 0
C_CTRL_AP_COL_CNT_LOAD_INDEX | 0
C_CTRL_AP_COL_CNT_ENABLE_INDEX | 0
C_CTRL_AP_PRECHARGE_ADDR10_INDEX | 0
C_CTRL_AP_ROW_COL_SEL_INDEX | 0
C_CTRL_PHYIF_FORCE_DM_INDEX | 0
C_CTRL_REPEAT4_INDEX | 0
C_CTRL_DFI_RAS_N_0_INDEX | 0
C_CTRL_DFI_CAS_N_0_INDEX | 0
C_CTRL_DFI_WE_N_0_INDEX | 0
C_CTRL_DFI_RAS_N_1_INDEX | 0
C_CTRL_DFI_CAS_N_1_INDEX | 0
C_CTRL_DFI_WE_N_1_INDEX | 0
C_CTRL_DP_WRFIFO_POP_INDEX | 0
C_CTRL_DFI_WRDATA_EN_INDEX | 0
C_CTRL_DFI_RDDATA_EN_INDEX | 0
C_CTRL_AP_OTF_ADDR12_INDEX | 0
C_CTRL_ARB_RDMODWR_DELAY | 0
C_CTRL_AP_COL_DELAY | 0
C_CTRL_AP_PI_ADDR_CE_DELAY | 0
C_CTRL_AP_PORT_SELECT_DELAY | 0
C_CTRL_AP_PIPELINE1_CE_DELAY | 0
C_CTRL_DP_LOAD_RDWDADDR_DELAY | 0
C_CTRL_DP_RDFIFO_WHICHPORT_DELAY | 0
C_CTRL_DP_SIZE_DELAY | 0
C_CTRL_DP_WRFIFO_WHICHPORT_DELAY | 0
C_CTRL_PHYIF_DUMMYREADSTART_DELAY | 0
C_CTRL_Q0_DELAY | 0
C_CTRL_Q1_DELAY | 0
C_CTRL_Q2_DELAY | 0
C_CTRL_Q3_DELAY | 0
C_CTRL_Q4_DELAY | 0
C_CTRL_Q5_DELAY | 0
C_CTRL_Q6_DELAY | 0
C_CTRL_Q7_DELAY | 0
C_CTRL_Q8_DELAY | 0
C_CTRL_Q9_DELAY | 0
C_CTRL_Q10_DELAY | 0
C_CTRL_Q11_DELAY | 0
C_CTRL_Q12_DELAY | 0
C_CTRL_Q13_DELAY | 0
C_CTRL_Q14_DELAY | 0
C_CTRL_Q15_DELAY | 0
C_CTRL_Q16_DELAY | 0
C_CTRL_Q17_DELAY | 0
C_CTRL_Q18_DELAY | 0
C_CTRL_Q19_DELAY | 0
C_CTRL_Q20_DELAY | 0
C_CTRL_Q21_DELAY | 0
C_CTRL_Q22_DELAY | 0
C_CTRL_Q23_DELAY | 0
C_CTRL_Q24_DELAY | 0
C_CTRL_Q25_DELAY | 0
C_CTRL_Q26_DELAY | 0
C_CTRL_Q27_DELAY | 0
C_CTRL_Q28_DELAY | 0
C_CTRL_Q29_DELAY | 0
C_CTRL_Q30_DELAY | 0
C_CTRL_Q31_DELAY | 0
C_CTRL_Q32_DELAY | 0
C_CTRL_Q33_DELAY | 0
C_CTRL_Q34_DELAY | 0
C_CTRL_Q35_DELAY | 0
C_SKIP_1_VALUE | 15
C_SKIP_2_VALUE | 15
C_SKIP_3_VALUE | 15
C_SKIP_4_VALUE | 20
C_SKIP_5_VALUE | 36
C_SKIP_6_VALUE | 20
C_SKIP_7_VALUE | 36
C_B16_REPEAT_CNT | 0
C_B32_REPEAT_CNT | 0
C_B64_REPEAT_CNT | 0
C_ZQCS_REPEAT_CNT | 0
C_BASEADDR_CTRL0 | 0x000
C_HIGHADDR_CTRL0 | 0x00D
C_BASEADDR_CTRL1 | 0x00E
C_HIGHADDR_CTRL1 | 0x017
C_BASEADDR_CTRL2 | 0x018
C_HIGHADDR_CTRL2 | 0x025
C_BASEADDR_CTRL3 | 0x026
C_HIGHADDR_CTRL3 | 0x02F
C_BASEADDR_CTRL4 | 0x030
C_HIGHADDR_CTRL4 | 0x03D
C_BASEADDR_CTRL5 | 0x03E
C_HIGHADDR_CTRL5 | 0x047
C_BASEADDR_CTRL6 | 0x048
C_HIGHADDR_CTRL6 | 0x05B
C_BASEADDR_CTRL7 | 0x05C
C_HIGHADDR_CTRL7 | 0x06A
C_BASEADDR_CTRL8 | 0x06B
C_HIGHADDR_CTRL8 | 0x086
C_BASEADDR_CTRL9 | 0x087
C_HIGHADDR_CTRL9 | 0x09D
C_BASEADDR_CTRL10 | 0x09E
C_HIGHADDR_CTRL10 | 0x0A5
C_BASEADDR_CTRL11 | 0x0A6
C_HIGHADDR_CTRL11 | 0x0AD
C_BASEADDR_CTRL12 | 0x0AE
C_HIGHADDR_CTRL12 | 0x0B5
C_BASEADDR_CTRL13 | 0x0B6
C_HIGHADDR_CTRL13 | 0x0BD
C_BASEADDR_CTRL14 | 0x0BE
C_HIGHADDR_CTRL14 | 0x0D0
C_BASEADDR_CTRL15 | 0x0D1
C_HIGHADDR_CTRL15 | 0x0D8
C_BASEADDR_CTRL16 | 0x0D9
C_HIGHADDR_CTRL16 | 0x0DA
C_CTRL_BRAM_INIT_3F | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3E | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3D | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3C | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3B | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_3A | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_39 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_38 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_37 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_36 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_35 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_34 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_33 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_32 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_31 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_30 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2F | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2E | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2D | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2C | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2B | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_2A | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_29 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_28 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_27 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_26 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_25 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_24 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_23 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_22 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_21 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_20 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1F | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1E | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1D | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1C | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1B | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_1A | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_19 | 0x000002FC000002FC000002FC000002FC000002FD000002FC000002FC000002FC
C_CTRL_BRAM_INIT_18 | 0x000002FC000002FC000002FC000002FC000002FC000002F0000002FC000002FC
C_CTRL_BRAM_INIT_17 | 0x000002FC000042E8000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_16 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_15 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_14 | 0x000002FC000002FC000002FC000002FC000002FC000002FC000002FC000002FC
C_CTRL_BRAM_INIT_13 | 0x000002FC000002FC000002FC000002FC000002FC000042E8000006FC000026F5
C_CTRL_BRAM_INIT_12 | 0x000006FC000026F4000006FC000026F4000006FC000026F4000006FC000026F4
C_CTRL_BRAM_INIT_11 | 0x000006FC000026F4000006FC000026F4000006FC000016F4000082FC000082FC
C_CTRL_BRAM_INIT_10 | 0x000082F8000002FC000002FC000002FC000042E8000002FC000002FD000002FC
C_CTRL_BRAM_INIT_0F | 0x000002FC000002FC0000093C000029240000093C000029240000093C00002924
C_CTRL_BRAM_INIT_0E | 0x0000093C000029240000093C000029240000093C000029240000093C00002924
C_CTRL_BRAM_INIT_0D | 0x0000093C000019240000803C000082FC000082F8000002FC000002FC000002FC
C_CTRL_BRAM_INIT_0C | 0x000042E8000006FC000026F5000006FC000026F4000006FC000026F4000006FC
C_CTRL_BRAM_INIT_0B | 0x000016F4000082FC000082FC000082F8000002FC000002FC000002FC000042E8
C_CTRL_BRAM_INIT_0A | 0x000002FC000002FD000002FC000002FC000002FC0000093C000029240000093C
C_CTRL_BRAM_INIT_09 | 0x000029240000093C000029240000093C000019240000803C000082FC000082F8
C_CTRL_BRAM_INIT_08 | 0x000002FC000002FC000002FC000042E8000002FC000006FD000016F4000082FC
C_CTRL_BRAM_INIT_07 | 0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD
C_CTRL_BRAM_INIT_06 | 0x000002FC000002FC000002FC0000093C000019240000803C000082FC000082F8
C_CTRL_BRAM_INIT_05 | 0x000002FC000002FC000002FC000042E8000002FC000002FD000016F4000082FC
C_CTRL_BRAM_INIT_04 | 0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD
C_CTRL_BRAM_INIT_03 | 0x000002FC000002FC000002FC0000013C000019240000803C000082FC000082F8
C_CTRL_BRAM_INIT_02 | 0x000002FC000002FC000002FC000042E8000002FC000002FD000016F4000082FC
C_CTRL_BRAM_INIT_01 | 0x000082FC000082F8000002FC000002FC000002FC000042E8000002FC000002FD
C_CTRL_BRAM_INIT_00 | 0x000002FC000002FC000002FC0000013C000019240000803C000082FC000082F8
C_CTRL_BRAM_SRVAL | 0x0000002FC
C_CTRL_BRAM_INITP_07 | 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_06 | 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_05 | 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_04 | 0x0000000000000000000000000000000000000000000000000000000000000000
C_CTRL_BRAM_INITP_03 | 0x0000000000000000000000000000000000000000000000001111111111111111
C_CTRL_BRAM_INITP_02 | 0x1110000000000000000000000000000000011111111111111111111111111111
C_CTRL_BRAM_INITP_01 | 0x1110000000000000000011111111111111111111111111000000000111111011
C_CTRL_BRAM_INITP_00 | 0x1111111111110001111110111111111111111001111110111111111111111001
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
bram_cntlr_0 LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus
IP Specs
Core | Version | Documentation
lmb_bram_if_cntlr | 3.00.c | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
TRANS_OUT | INITIATOR | CUSTOM_FIFO | bram_cntlr_0_TRANS_OUT | bram_cntlr_1
BRAM_PORT | INITIATOR | XIL_BRAM | bram_cntlr_0_BRAM_PORT | lmb_bram_0
BRAM_PORT_1 | INITIATOR | XIL_BRAM | bram_cntlr_0_BRAM_PORT_1 | lmb_bram_0
SLMB | SLAVE | LMB | dlmb_0 | microblaze_0
SLMB_1 | SLAVE | LMB | ilmb_0 | microblaze_0
RCV_IN | TARGET | CUSTOM_FIFO | bram_cntlr_3_TRANS_OUT | bram_cntlr_3
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_BASEADDR | 0x00000000
C_HIGHADDR | 0x0000FFFF
C_FAMILY | virtex5
C_MASK | 0x80000000
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_ECC | 0
C_INTERCONNECT | 0
C_FAULT_INJECT | 0
C_CE_FAILING_REGISTERS | 0
C_UE_FAILING_REGISTERS | 0
C_ECC_STATUS_REGISTERS | 0
C_ECC_ONOFF_REGISTER | 0
C_ECC_ONOFF_RESET_VALUE | 1
C_CE_COUNTER_WIDTH | 0
C_WRITE_ACCESS | 2 |  | Name | Value
C_SPLB_CTRL_BASEADDR | 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR | 0x00000000
C_SPLB_CTRL_AWIDTH | 32
C_SPLB_CTRL_DWIDTH | 32
C_SPLB_CTRL_P2P | 0
C_SPLB_CTRL_MID_WIDTH | 1
C_SPLB_CTRL_NUM_MASTERS | 1
C_SPLB_CTRL_SUPPORT_BURSTS | 0
C_SPLB_CTRL_NATIVE_DWIDTH | 32
C_SPLB_CTRL_CLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_BASEADDR | 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR | 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_S_AXI_CTRL_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
bram_cntlr_1 LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus
IP Specs
Core | Version | Documentation
lmb_bram_if_cntlr | 3.00.c | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
TRANS_OUT | INITIATOR | CUSTOM_FIFO | bram_cntlr_1_TRANS_OUT | bram_cntlr_2
BRAM_PORT | INITIATOR | XIL_BRAM | bram_cntlr_1_BRAM_PORT | lmb_bram_1
BRAM_PORT_1 | INITIATOR | XIL_BRAM | bram_cntlr_1_BRAM_PORT_1 | lmb_bram_1
SLMB | SLAVE | LMB | dlmb_1 | microblaze_1
SLMB_1 | SLAVE | LMB | ilmb_1 | microblaze_1
RCV_IN | TARGET | CUSTOM_FIFO | bram_cntlr_0_TRANS_OUT | bram_cntlr_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_BASEADDR | 0x00000000
C_HIGHADDR | 0x0000FFFF
C_FAMILY | virtex5
C_MASK | 0x80000000
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_ECC | 0
C_INTERCONNECT | 0
C_FAULT_INJECT | 0
C_CE_FAILING_REGISTERS | 0
C_UE_FAILING_REGISTERS | 0
C_ECC_STATUS_REGISTERS | 0
C_ECC_ONOFF_REGISTER | 0
C_ECC_ONOFF_RESET_VALUE | 1
C_CE_COUNTER_WIDTH | 0
C_WRITE_ACCESS | 2 |  | Name | Value
C_SPLB_CTRL_BASEADDR | 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR | 0x00000000
C_SPLB_CTRL_AWIDTH | 32
C_SPLB_CTRL_DWIDTH | 32
C_SPLB_CTRL_P2P | 0
C_SPLB_CTRL_MID_WIDTH | 1
C_SPLB_CTRL_NUM_MASTERS | 1
C_SPLB_CTRL_SUPPORT_BURSTS | 0
C_SPLB_CTRL_NATIVE_DWIDTH | 32
C_SPLB_CTRL_CLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_BASEADDR | 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR | 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_S_AXI_CTRL_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
bram_cntlr_2 LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus
IP Specs
Core | Version | Documentation
lmb_bram_if_cntlr | 3.00.c | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
TRANS_OUT | INITIATOR | CUSTOM_FIFO | bram_cntlr_2_TRANS_OUT | bram_cntlr_3
BRAM_PORT | INITIATOR | XIL_BRAM | bram_cntlr_2_BRAM_PORT | lmb_bram_2
BRAM_PORT_1 | INITIATOR | XIL_BRAM | bram_cntlr_2_BRAM_PORT_1 | lmb_bram_2
SLMB | SLAVE | LMB | dlmb_2 | microblaze_2
SLMB_1 | SLAVE | LMB | ilmb_2 | microblaze_2
RCV_IN | TARGET | CUSTOM_FIFO | bram_cntlr_1_TRANS_OUT | bram_cntlr_1
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_BASEADDR | 0x00000000
C_HIGHADDR | 0x0000FFFF
C_FAMILY | virtex5
C_MASK | 0x80000000
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_ECC | 0
C_INTERCONNECT | 0
C_FAULT_INJECT | 0
C_CE_FAILING_REGISTERS | 0
C_UE_FAILING_REGISTERS | 0
C_ECC_STATUS_REGISTERS | 0
C_ECC_ONOFF_REGISTER | 0
C_ECC_ONOFF_RESET_VALUE | 1
C_CE_COUNTER_WIDTH | 0
C_WRITE_ACCESS | 2 |  | Name | Value
C_SPLB_CTRL_BASEADDR | 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR | 0x00000000
C_SPLB_CTRL_AWIDTH | 32
C_SPLB_CTRL_DWIDTH | 32
C_SPLB_CTRL_P2P | 0
C_SPLB_CTRL_MID_WIDTH | 1
C_SPLB_CTRL_NUM_MASTERS | 1
C_SPLB_CTRL_SUPPORT_BURSTS | 0
C_SPLB_CTRL_NATIVE_DWIDTH | 32
C_SPLB_CTRL_CLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_BASEADDR | 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR | 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_S_AXI_CTRL_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
bram_cntlr_3 LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus
IP Specs
Core | Version | Documentation
lmb_bram_if_cntlr | 3.00.c | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
BRAM_PORT | INITIATOR | XIL_BRAM | bram_cntlr_3_BRAM_PORT | lmb_bram_3
BRAM_PORT_1 | INITIATOR | XIL_BRAM | bram_cntlr_3_BRAM_PORT_1 | lmb_bram_3
TRANS_OUT | INITIATOR | CUSTOM_FIFO | bram_cntlr_3_TRANS_OUT | bram_cntlr_0
SLMB | SLAVE | LMB | dlmb_3 | microblaze_3
SLMB_1 | SLAVE | LMB | ilmb_3 | microblaze_3
RCV_IN | TARGET | CUSTOM_FIFO | bram_cntlr_2_TRANS_OUT | bram_cntlr_2
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_BASEADDR | 0x00000000
C_HIGHADDR | 0x0000FFFF
C_FAMILY | virtex5
C_MASK | 0x80000000
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_ECC | 0
C_INTERCONNECT | 0
C_FAULT_INJECT | 0
C_CE_FAILING_REGISTERS | 0
C_UE_FAILING_REGISTERS | 0
C_ECC_STATUS_REGISTERS | 0
C_ECC_ONOFF_REGISTER | 0
C_ECC_ONOFF_RESET_VALUE | 1
C_CE_COUNTER_WIDTH | 0
C_WRITE_ACCESS | 2 |  | Name | Value
C_SPLB_CTRL_BASEADDR | 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR | 0x00000000
C_SPLB_CTRL_AWIDTH | 32
C_SPLB_CTRL_DWIDTH | 32
C_SPLB_CTRL_P2P | 0
C_SPLB_CTRL_MID_WIDTH | 1
C_SPLB_CTRL_NUM_MASTERS | 1
C_SPLB_CTRL_SUPPORT_BURSTS | 0
C_SPLB_CTRL_NATIVE_DWIDTH | 32
C_SPLB_CTRL_CLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_BASEADDR | 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR | 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_S_AXI_CTRL_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
kernel_bram_if_cntlr XPS BRAM Controller Attaches BRAM to the PLBV46
IP Specs
Core | Version | Documentation
xps_bram_if_cntlr | 1.00.b | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
PORTA | INITIATOR | XIL_BRAM | kernel_bram_if_cntlr_PORTA | kernel_bram
SPLB | SLAVE | PLBV46 | shared_plb | 7 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_BASEADDR | 0x84410000
C_HIGHADDR | 0x84410FFF
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_NUM_MASTERS | 2 |  | Name | Value
C_SPLB_MID_WIDTH | 1
C_SPLB_SUPPORT_BURSTS | 1
C_SPLB_P2P | 0
C_SPLB_SMALLEST_MASTER | 32
C_FAMILY | virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Peripherals | TOP
RS232_Uart_1 XPS UART (Lite) Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.
IP Specs
Core | Version | Documentation
xps_uartlite | 1.02.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | RX | I | 1 | fpga_0_RS232_Uart_1_RX_pin
1 | TX | O | 1 | fpga_0_RS232_Uart_1_TX_pin
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
SPLB | SLAVE | PLBV46 | shared_plb | 7 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex5
C_SPLB_CLK_FREQ_HZ | 100000000
C_BASEADDR | 0x84000000
C_HIGHADDR | 0x8400FFFF
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_P2P | 0
C_SPLB_MID_WIDTH | 1 |  | Name | Value
C_SPLB_NUM_MASTERS | 1
C_SPLB_SUPPORT_BURSTS | 0
C_SPLB_NATIVE_DWIDTH | 32
C_BAUDRATE | 9600
C_DATA_BITS | 8
C_USE_PARITY | 0
C_ODD_PARITY | 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
SysACE_CompactFlash XPS System ACE Interface Controller(Compact Flash) Interface between the PLBV46 and the Microprocessor Interface (MPU) of the System ACE Compact Flash solution peripheral
IP Specs
Core | Version | Documentation
xps_sysace | 1.01.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | SysACE_MPA | O | 1 | SysACE_CompactFlash_SysACE_MPA
1 | SysACE_CLK | I | 1 | SysACE_CompactFlash_SysACE_CLK
2 | SysACE_MPIRQ | I | 1 | SysACE_CompactFlash_SysACE_MPIRQ
3 | SysACE_CEN | O | 1 | SysACE_CompactFlash_SysACE_CEN
4 | SysACE_OEN | O | 1 | SysACE_CompactFlash_SysACE_OEN
5 | SysACE_WEN | O | 1 | SysACE_CompactFlash_SysACE_WEN
6 | SysACE_MPD | IO | 1 | SysACE_CompactFlash_SysACE_MPD
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
SPLB | SLAVE | PLBV46 | shared_plb | 7 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_BASEADDR | 0x85000000
C_HIGHADDR | 0x8500FFFF
C_MEM_WIDTH | 16
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_P2P | 0 |  | Name | Value
C_SPLB_MID_WIDTH | 3
C_SPLB_NUM_MASTERS | 8
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_SUPPORT_BURSTS | 0
C_FAMILY | virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
fsl_timer_0
IP Specs
Core | Version
fsl_timer | 1.00.a
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
MFSL_0 | MASTER | FSL | fsl_tmr_to_mb0 | microblaze_0
MFSL_1 | MASTER | FSL | fsl_tmr_to_mb1 | microblaze_1
MFSL_2 | MASTER | FSL | fsl_tmr_to_mb2 | microblaze_2
MFSL_3 | MASTER | FSL | fsl_tmr_to_mb3 | microblaze_3
SFSL_0 | SLAVE | FSL | fsl_mb0_to_tmr | microblaze_0
SFSL_1 | SLAVE | FSL | fsl_mb1_to_tmr | microblaze_1
SFSL_2 | SLAVE | FSL | fsl_mb2_to_tmr | microblaze_2
SFSL_3 | SLAVE | FSL | fsl_mb3_to_tmr | microblaze_3
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
shared_mutex
IP Specs
Core | Version
user_mutex | 1.00.a
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
MFSL_1 | MASTER | FSL | fsl_mutex_to_mb1 | microblaze_1
MFSL_2 | MASTER | FSL | fsl_mutex_to_mb2 | microblaze_2
MFSL_3 | MASTER | FSL | fsl_mutex_to_mb3 | microblaze_3
MFSL_0 | MASTER | FSL | fsl_mutex_to_mb0 | microblaze_0
SFSL_1 | SLAVE | FSL | fsl_mb1_to_mutex | microblaze_1
SFSL_2 | SLAVE | FSL | fsl_mb2_to_mutex | microblaze_2
SFSL_3 | SLAVE | FSL | fsl_mb3_to_mutex | microblaze_3
SFSL_0 | SLAVE | FSL | fsl_mb0_to_mutex | microblaze_0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
IP | TOP
clock_generator_0 Clock Generator Clock generator for processor system.
IP Specs
Core | Version | Documentation
clock_generator | 4.03.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | CLKIN | I | 1 | CLK_S
1 | CLKOUT1 | O | 1 | clk_166_6667MHz90PLL0
2 | CLKOUT2 | O | 1 | clk_166_6667MHzPLL0
3 | RST | I | 1 | sys_rst_s
4 | LOCKED | O | 1 | Dcm_all_locked
5 | PSDONE | O | 1 | clock_generator_0_PSDONE
6 | CLKOUT3 | O | 1 | clk_200_0000MHz
7 | CLKOUT4 | O | 1 | clk_83_3333MHzPLL0
8 | CLKOUT0 | O | 1 | clk_100_0000MHz
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_DEVICE | NOT_SET
C_PACKAGE | NOT_SET
C_SPEEDGRADE | NOT_SET
C_CLKIN_FREQ | 100000000
C_CLKOUT0_FREQ | 100000000
C_CLKOUT0_PHASE | 0
C_CLKOUT0_GROUP | NONE
C_CLKOUT0_BUF | TRUE
C_CLKOUT0_VARIABLE_PHASE | FALSE
C_CLKOUT1_FREQ | 166666666
C_CLKOUT1_PHASE | 90
C_CLKOUT1_GROUP | PLL0
C_CLKOUT1_BUF | TRUE
C_CLKOUT1_VARIABLE_PHASE | FALSE
C_CLKOUT2_FREQ | 166666666
C_CLKOUT2_PHASE | 0
C_CLKOUT2_GROUP | PLL0
C_CLKOUT2_BUF | TRUE
C_CLKOUT2_VARIABLE_PHASE | FALSE
C_CLKOUT3_FREQ | 200000000
C_CLKOUT3_PHASE | 0
C_CLKOUT3_GROUP | NONE
C_CLKOUT3_BUF | TRUE
C_CLKOUT3_VARIABLE_PHASE | FALSE
C_CLKOUT4_FREQ | 83333333
C_CLKOUT4_PHASE | 0
C_CLKOUT4_GROUP | PLL0
C_CLKOUT4_BUF | TRUE
C_CLKOUT4_VARIABLE_PHASE | FALSE
C_CLKOUT5_FREQ | 0
C_CLKOUT5_PHASE | 0
C_CLKOUT5_GROUP | NONE
C_CLKOUT5_BUF | TRUE
C_CLKOUT5_VARIABLE_PHASE | FALSE
C_CLKOUT6_FREQ | 0
C_CLKOUT6_PHASE | 0
C_CLKOUT6_GROUP | NONE
C_CLKOUT6_BUF | TRUE
C_CLKOUT6_VARIABLE_PHASE | FALSE
C_CLKOUT7_FREQ | 0
C_CLKOUT7_PHASE | 0
C_CLKOUT7_GROUP | NONE
C_CLKOUT7_BUF | TRUE
C_CLKOUT7_VARIABLE_PHASE | FALSE
C_CLKOUT8_FREQ | 0
C_CLKOUT8_PHASE | 0
C_CLKOUT8_GROUP | NONE
C_CLKOUT8_BUF | TRUE
C_CLKOUT8_VARIABLE_PHASE | FALSE
C_CLKOUT9_FREQ | 0
C_CLKOUT9_PHASE | 0
C_CLKOUT9_GROUP | NONE
C_CLKOUT9_BUF | TRUE
C_CLKOUT9_VARIABLE_PHASE | FALSE
C_CLKOUT10_FREQ | 0 |  | Name | Value
C_CLKOUT10_PHASE | 0
C_CLKOUT10_GROUP | NONE
C_CLKOUT10_BUF | TRUE
C_CLKOUT10_VARIABLE_PHASE | FALSE
C_CLKOUT11_FREQ | 0
C_CLKOUT11_PHASE | 0
C_CLKOUT11_GROUP | NONE
C_CLKOUT11_BUF | TRUE
C_CLKOUT11_VARIABLE_PHASE | FALSE
C_CLKOUT12_FREQ | 0
C_CLKOUT12_PHASE | 0
C_CLKOUT12_GROUP | NONE
C_CLKOUT12_BUF | TRUE
C_CLKOUT12_VARIABLE_PHASE | FALSE
C_CLKOUT13_FREQ | 0
C_CLKOUT13_PHASE | 0
C_CLKOUT13_GROUP | NONE
C_CLKOUT13_BUF | TRUE
C_CLKOUT13_VARIABLE_PHASE | FALSE
C_CLKOUT14_FREQ | 0
C_CLKOUT14_PHASE | 0
C_CLKOUT14_GROUP | NONE
C_CLKOUT14_BUF | TRUE
C_CLKOUT14_VARIABLE_PHASE | FALSE
C_CLKOUT15_FREQ | 0
C_CLKOUT15_PHASE | 0
C_CLKOUT15_GROUP | NONE
C_CLKOUT15_BUF | TRUE
C_CLKOUT15_VARIABLE_PHASE | FALSE
C_CLKFBIN_FREQ | 0
C_CLKFBIN_DESKEW | NONE
C_CLKFBOUT_FREQ | 0
C_CLKFBOUT_PHASE | 0
C_CLKFBOUT_GROUP | NONE
C_CLKFBOUT_BUF | TRUE
C_PSDONE_GROUP | NONE
C_EXT_RESET_HIGH | 0
C_CLK_PRIMITIVE_FEEDBACK_BUF | FALSE
C_CLKOUT0_DUTY_CYCLE | 0.500000
C_CLKOUT1_DUTY_CYCLE | 0.500000
C_CLKOUT2_DUTY_CYCLE | 0.500000
C_CLKOUT3_DUTY_CYCLE | 0.500000
C_CLKOUT4_DUTY_CYCLE | 0.500000
C_CLKOUT5_DUTY_CYCLE | 0.500000
C_CLKOUT6_DUTY_CYCLE | 0.500000
C_CLKOUT7_DUTY_CYCLE | 0.500000
C_CLKOUT8_DUTY_CYCLE | 0.500000
C_CLKOUT9_DUTY_CYCLE | 0.500000
C_CLKOUT10_DUTY_CYCLE | 0.500000
C_CLKOUT11_DUTY_CYCLE | 0.500000
C_CLKOUT12_DUTY_CYCLE | 0.500000
C_CLKOUT13_DUTY_CYCLE | 0.500000
C_CLKOUT14_DUTY_CYCLE | 0.500000
C_CLKOUT15_DUTY_CYCLE | 0.500000
C_CLK_GEN | UPDATE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
proc_sys_reset_0 Processor System Reset Module Reset management module
IP Specs
Core | Version | Documentation
proc_sys_reset | 3.00.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | Slowest_sync_clk | I | 1 | clk_83_3333MHzPLL0
1 | Ext_Reset_In | I | 1 | sys_rst_s
2 | MB_Debug_Sys_Rst | I | 1 | Debug_SYS_Rst
3 | Dcm_locked | I | 1 | Dcm_all_locked
4 | MB_Reset | O | 1 | mb_reset
5 | Bus_Struct_Reset | O | 1 | sys_bus_reset
6 | Peripheral_Reset | O | 1 | sys_periph_reset
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_SUBFAMILY | lx
C_EXT_RST_WIDTH | 4
C_AUX_RST_WIDTH | 4
C_EXT_RESET_HIGH | 0
C_AUX_RESET_HIGH | 1
C_NUM_BUS_RST | 1
C_NUM_PERP_RST | 1
C_NUM_INTERCONNECT_ARESETN | 1
C_NUM_PERP_ARESETN | 1
C_FAMILY | virtex5 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Timing Information | TOP Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.