* [[http://blog.csdn.net/muxiqingyang/article/details/6627096|大话处理器]]
  * [[http://www.morganclaypool.com/toc/cac/5/1|Synthesis Lectures on Computer Architecture]]

定義 ISA 包含定義以下東西:
  - 處理器狀態: 暫存器和內存。暫存器一般又分通用暫存器、條件碼、程式計數器和狀態碼。狀態碼紀錄程序是正常運行還是有異常發生。
  - 指令集和其編碼: 指令集定義的指令操作處理器狀態。一般有底下幾類: 傳送 (move)，算術運算，跳轉，條件傳送，call，棧操作指令 (push/pop) 和 halt。
  - 編程規範: 例如 calling convention。
  - 異常處理

<code bash>
$ wget http://csapp.cs.cmu.edu/public/sim.tar; tar xvf sim.tar; cd sim
# 註解掉 Makefile 裡面底下幾行，不用 GUI。
# TKLIBS=-L/usr/lib -ltk -ltcl
# TKINC=-isystem /usr/include 
$ make
</code>
====== 術語 ======
  * [[http://blog.mcuol.com/User/AT91RM9200/Article/40353_1.htm|冯·诺依曼结构和哈佛结构]]
  * [[wp>Program status word (PSW)]] 或稱 [[wp>Status register]]。
  * [[wp>Branch predictor]]
    * Branch Target Buffer (BTB)
    * Return Address Stack (RAS)
    * [[http://blog.csdn.net/muxiqingyang/article/details/6680315|《大话处理器》连载——微架构(9) 分支预测——以古为镜，可以知兴替]]
  * [[wp>Out-of-order execution]]
    * [[wp>Tomasulo algorithm]] 
    * [[wp>Register renaming]]
      * 去除指令之間的相依性。 
    * [[wp>Reservation stations]]
    * [[wp>Re-order buffer|Re-order buffer (ROB)]]
      * 負責 in-order commit。
    * [[wp>Memory disambiguation]]
    * [[http://www.pcguide.com/ref/mbsys/cache/charTransactional-c.html|Non-Blocking Cache]]
    * [[http://blog.csdn.net/muxiqingyang/article/details/6692735|《大话处理器》连载——微架构(12) 指令的相关]]
  * [[wp>System-on-a-chip|System On Chip (SOC)]]
    * 處理器 (一般稱 [[wp>Semiconductor intellectual property core|IP]])、內存和之間的連接 (interconnect)。
    * [[wp>HyperTransport]]
    * [[wp>Advanced Microcontroller Bus Architecture]]
      * ARM SOC Bus。
     * [[wp>Network On Chip|Network On Chip (NOC)]]
       * 為 interconnect 的一種方式，有別於傳統的 bus，點和點之間用 switch 直接或間接互連。
     * [[wp>Crossbar switch|Crossbar]]
      * 點和點之間直接互連。比 NOC 耗錢，但較快速。 
  * [[wp>Memory management unit|Memory management unit (MMU)]]
    * MMU 是處理器內部的硬件，負責虛擬地址和物理地址的翻譯，同時也在 TLB 缺失的時候負責查詢頁表。
  * [[wp>CPU cache]]
    * Physically indexed, physically tagged (PIPT) caches
    * Virtually indexed, virtually tagged (VIVT) caches
  * [[wp>Interrupt]]
    * Level-triggered
    * Edge-triggered
  * [[wp>Watchdog timer]]
    * <q>During normal operation, the computer regularly restarts the watchdog timer to prevent it from elapsing, or "timing out". If, due to a hardware fault or program error, the computer fails to restart the watchdog, the timer will elapse and generate a timeout signal.</q>
    * [[http://forum.eettaiwan.com/FORUM_POST_1000039157_1200047570_0.HTM?jumpto=view_welcomead_forum_1414998319962|請教一下Watch Dog！？]]
    * 正常情況下，應該要重設 watchdog timer。如果因為軟硬體錯誤，導致 watchdog timer 未被重設，一定時間過後，watchdog timer 會發出 timeout signal，一般會導致系統重置 (reset)。
====== 文章 ======
  * [[http://www.morganclaypool.com/toc/cac/5/1|Synthesis Lectures on Computer Architecture]]
====== 外部連結 ======
  * [[http://csapp.cs.cmu.edu/|Computer Systems: A Programmer's Perspective]]
    * [[http://csapp.cs.cmu.edu/public/students.html]]
  * [[http://www.amazon.cn/Computers-as-Components-Second-Edition-Principles-of-Embedded-Computing-System-Design-Wolf-Wayne/dp/0123743974|Computers as Components, Second Edition: Principles of Embedded Computing System Design]]
    * [[http://www.waynewolf.us/]]
  * [[http://www.amazon.com/Computer-System-Design-System-Chip/dp/0470643366|Computer System Design: System-on-Chip]]
  * [[http://www.csie.ntu.edu.tw/~hungsh/CA/ca.htm|計算機系統結構]]
  * [[http://people.ee.duke.edu/~sorin/ece252/|Advanced Computer Architecture I]]
  * [[http://booksite.mkp.com/9780123838728/index.php|Computer Architecture: A Quantitative Approach 5e]]
  * [[http://www.tektalk.org/2011/10/04/%e5%bc%af%e6%9b%b2%e8%af%84%e8%ae%ba%e8%8d%a3%e8%aa%89%e5%87%ba%e5%93%81%ef%bc%9a%e3%80%8a%e6%b5%85%e8%b0%88cache-memory%e3%80%8b/|淺談 Cache Memory]]
  * [[http://www.cast.org.cn/n35081/n11219166/n12620949/n12621051/13019136.html|The Godson Processors: Its Research, Development, and Contributions]]
  * [[http://www.ltivs.ilc.edu.tw/kocp/|數位邏輯]]